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RL78 Datasheet(PDF) 75 Page - Renesas Technology Corp

Part # RL78
Description  True Low Power Platform (as low as 66 ?쵡/MHz, and 0.60 ?쵡 for RTC LVD), 1.6 V to 5.5 V operation
PDF  100 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RL78 Datasheet(HTML) 75 Page - Renesas Technology Corp

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RL78/G14
2. ELECTRICAL SPECIFICATIONS
R01DS0053EJ0100 Rev. 1.00
Page 75 of 97
Feb 21, 2012
Caution
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(Notes, Caution and Remarks are listed on the next page.)
(7)
Communication at different potential (2.5 V, 3 V) (fMCK/2) (CSI mode) (master mode, SCKp... internal clock output)
(TA = -40 to +85
C, 2.7 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCKp cycle time
tKCY1
4.0 V
 EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
200 Note 1
ns
2.7 V
 EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
300 Note 1
ns
SCKp high-level width
tKH1
4.0 V
 EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
tKCY1/2 - 50
ns
2.7 V
 EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
tKCY1/2 - 120
ns
SCKp low-level width
tKL1
4.0 V
 EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
tKCY1/2 - 7
ns
2.7 V
 EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
tKCY1/2 - 10
ns
SIp setup time
(to SCKp
↑) Note 2
tSIK1
4.0 V
 EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
58
ns
2.7 V
 EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
121
ns
SIp hold time
(from SCKp
↑) Note 2
tKSI1
4.0 V
 EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
10
ns
2.7 V
 EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
10
ns
Delay time from SCKp
↓ to SOp
output Note 2
tKSO1
4.0 V
 EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
60
ns
2.7 V
 EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
130
ns
SIp setup time
(to SCKp
↓) Note 3
tSIK1
4.0 V
 EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
23
ns
2.7 V
 EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
33
ns
SIp hold time
(from SCKp
↓) Note 3
tKSI1
4.0 V
 EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
10
ns
2.7 V
 EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
10
ns
Delay time from SCKp
↑ to SOp
output Note 3
tKSO1
4.0 V
 EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
10
ns
2.7 V
 EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
10
ns



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