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RL78 Datasheet(PDF) 96 Page - Renesas Technology Corp |
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RL78 Datasheet(HTML) 96 Page - Renesas Technology Corp |
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96 / 100 page ![]() RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 96 of 97 Feb 21, 2012 Caution The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products. 2.7 Power Supply Rise Time 2.8 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is effected, but data is not retained when a POR reset is effected. 2.9 Flash Memory Programming Characteristics Note When using flash memory programmer and Renesas Electronics self programming library. Remark When updating data multiple times, use the flash memory as one for updating data. (TA = -40 to +85 C, VSS = EVSS0 = EVSS1 = 0 V) Parameter Conditions MIN. TYP. MAX. Unit VDD rise inclination TPUP 53.0 V/ms (TA = -40 to +85 C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention supply voltage VDDDR 1.5 Note 5.5 V (TA = -40 to +85 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit CPU/peripheral hardware clock frequency fCLK 1.8 V VDD 5.5 V 132 MHz Number of code flash rewrites Cerwr 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. Retained for 20 years (Self/serial programming) Note 1,000 Times Number of data flash rewrites Retained for 1 years (Self/serial programming) Note 1,000,000 Retained for 5 years (Self/serial programming) Note 100,000 VDD STOP instruction execution Standby release signal (interrupt request) STOP mode Data retention mode Operation mode VDDDR |
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