MICRF505L datasheet(13/43 Pages) MICREL

13 / 43 page

Micrel

MICRF505BML/YML

August 2006

M9999-092904

+1 408-944-0800

Symbol

Parameter

Min.

Typ.

Max.

Units

Tper

Min. period of SCLK

Thigh

Min. high time of SCLK

Tlow

Min. low time of SCLK

tfall

Max. time of falling edge of SCLK

µs

trise

Max. time of rising edge of SCLK

µs

Tcsr

Max. time of rising edge of CS to falling edge of SCLK

Tcsf

Min. delay from rising edge of CS to rising edge of

SCLK

Twrite

Min. delay from valid IO to falling edge of SCLK

during a write operation

Tread

Min. delay from rising edge of SCLK to valid IO during

a read operation (assuming load capacitance of IO is

25pF)

POR

Power on Reset delay from voltage is supplied to he

device until POR completed

4.6

Table 6. Timing Specification for the 3-wire Programming Interface

Power on Reset

When applying voltage to the MICRF505 a power

on reset state is entered. During the time period of

power

reset,

the

MICRF505

should

considered to be in an unknown state and the user

should wait until completed (See Table 6). The

power on reset timing given in table 6 is covering all

conditions and should be treated as a maximum

delay time. In some application it might be beneficial

to minimize the power on reset time. In these cases

we recommend to follow below procedure:

Program

address 0x00

Word:0x03

Read back

programmed

address 0x00

Value=0x03?

End of Power on

Reset

YES

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