AD5686R datasheet(22/32 Pages) AD

22 / 32 page

AD5686R/AD5685R/AD5684R

Data Sheet

Rev. 0 | Page 22 of 32

STANDALONE OPERATION

The write sequence begins by bringing the SYNC line low. Data

from the SDIN line is clocked into the 24-bit input shift register

on the falling edge of SCLK. After the last of 24 data bits is

clocked in, SYNC should be brought high. The programmed

function is then executed, that is, an LDAC-dependent change

in DAC register contents and/or a change in the mode of

operation. If SYNC is taken high at a clock before the 24th clock,

it is considered a valid frame and invalid data may be loaded to

the DAC. SYNC must be brought high for a minimum of

20 ns (single channel, see t8 in Figure 2) before the next write

sequence so that a falling edge of SYNC can initiate the next

write sequence. SYNC should be idled at rails between write

sequences for even lower power operation of the part.

The SYNC line is kept low for 24 falling edges of SCLK, and the

DAC is updated on the rising edge of SYNC.

When the data has been transferred into the input register of

the addressed DAC, all DAC registers and outputs can be

updated by taking LDAC low while the SYNC line is high.

WRITE AND UPDATE COMMANDS

Write to Input Register n (Dependent on LDAC)

Command 0001 allows the user to write to each DAC’s

dedicated input register individually. When LDAC is low,

the input register is transparent (if not controlled by the

LDAC mask register).

Update DAC Register n with Contents of Input Register n

Command 0010 loads the DAC registers/outputs with the

contents of the input registers selected and updates the DAC

outputs directly.

Write to and Update DAC Channel n (Independent of

LDAC)

Command 0011 allows the user to write to the DAC registers

and update the DAC outputs directly.

AD5686R Datasheet(PDF) 22 Page - Analog Devices