AD586 datasheet(32/44 Pages) AD

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AD5737

Data Sheet

Rev. B | Page 32 of 44

DEVICE FEATURES

FAULT OUTPUT

The AD5737 is equipped with a FAULT pin, an active low,

open-drain output that allows several AD5737 devices to be

connected together to one pull-up resistor for global fault

detection. The FAULT pin is forced active by any one of the

following fault conditions:

•

The voltage at IOUT_x attempts to rise above the compliance

range due to an open-loop circuit or insufficient power

supply voltage. The internal circuitry that develops the

fault output avoids using a comparator with windowed

limits because this requires an actual output error before

the FAULT output becomes active. Instead, the signal is

generated when the internal amplifier in the output stage

has less than approximately 1 V of remaining drive

capability. Thus, the FAULT output is activated slightly

before the compliance limit is reached.

•

An interface error is detected due to a PEC failure (see the

Packet Error Checking section).

•

The core temperature of the AD5737 exceeds approxi-

mately 150°C.

The IOUT_x fault, PEC error, and over temp bits of the status

inform the user which fault condition caused the FAULT

output to be activated.

DIGITAL OFFSET AND GAIN CONTROL

Each DAC channel has a gain (M) register and an offset (C)

of the entire signal chain. Data from the DAC data register is

operated on by a digital multiplier and adder controlled by the

contents of the gain and offset registers; the calibrated DAC

data is then stored in the DAC input register (see Figure 52).

DAC

INPUT

DAC

DAC DATA

GAIN (M)

OFFSET (C)

Figure 52. Digital Offset and Gain Control

Although Figure 52 indicates a multiplier and adder for each

channel, the device has only one multiplier and one adder,

which are shared by all four channels. This design has impli-

cations for the update speed when several channels are updated

at once (see Table 3).

When data is written to the gain (M) or offset (C) register, the

output is not automatically updated. Instead, the next write to

the DAC channel uses the new gain and offset values to perform

a new calibration and automatically updates the channel.

The output data from the calibration is routed to the DAC input

Serial Interface section. Both the gain register and the offset

the gain and offset is to first calibrate the gain and then calibrate

the offset.

The value (in decimal) that is written to the DAC input register

can be calculated as follows:

)

(

−

Code

DACRegiste

(1)

where:

D is the code loaded to the DAC data register of the

DAC channel.

M is the code in the gain register (default code = 212 − 1).

C is the code in the offset register (default code = 211).

STATUS READBACK DURING A WRITE

The AD5737 can be configured to read back the contents of

the status register during every write sequence. This feature is

enabled using the STATREAD bit in the main control register.

When this feature is enabled, the user can continuously monitor

the status register and act quickly in the case of a fault.

When status readback during a write is enabled, the contents

of the 16-bit status register (see Table 32) are output on the SDO

pin, as shown in Figure 5.

When the AD5737 is powered up, the status readback during a

write feature is disabled. When this feature is enabled, readback

of registers other than the status register is not available. To read

back any other register, clear the STATREAD bit before following

the readback sequence (see the Readback Operation section).

The STATREAD bit can be set high again after the register read.

ASYNCHRONOUS CLEAR

CLEAR is an active high, edge sensitive input that allows the

output to be cleared to a preprogrammed 12-bit code. This code

is user-programmable via a per-channel 12-bit clear code register.

For a channel to be cleared, set the CLR_EN bit in the DAC

control register for that channel. If the clear function on a

channel is not enabled, the output remains in its current state,

independent of the level of the CLEAR pin.

When the CLEAR signal returns low, the relevant outputs remain

cleared until a new value is programmed to them.

AD586 Datasheet(PDF) 32 Page - Analog Devices

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