AD586 datasheet(33/44 Pages) AD

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Data Sheet

AD5737

Rev. B | Page 33 of 44

PACKET ERROR CHECKING

To verify that data has been received correctly in noisy environ-

ments, the AD5737 offers the option of packet error checking

based on an 8-bit cyclic redundancy check (CRC-8). The device

controlling the AD5737 should generate an 8-bit frame check

sequence using the following polynomial:

C(x) = x8 + x2 + x1 + 1

This value is added to the end of the data-word, and 32 bits are

sent to the AD5737 before SYNC goes high. If the AD5737 sees a

32-bit frame, it performs the error check when SYNC goes high.

If the error check is valid, the data is written to the selected register.

If the error check fails, the FAULT pin goes low and the PEC error

bit in the status register is set. After the status register is read,

FAULT returns high (assuming that there are no other faults),

and the PEC error bit is cleared automatically.

SDIN

SYNC

SCLK

UPDATE ON SYNC HIGH

MSB

D23

LSB

24-BIT DATA

24-BIT DATA TRANSFER—NO ERROR CHECKING

SDIN

FAULT

SYNC

SCLK

ONLY IF ERROR CHECK PASSED

FAULT PIN GOES LOW

IF ERROR CHECK FAILS

MSB

D31

LSB

24-BIT DATA

8-BIT CRC

32-BIT DATA TRANSFER WITH ERROR CHECKING

UPDATE ON SYNC HIGH

Figure 53. PEC Timing

Packet error checking can be used for transmitting and receiv-

ing data packets. If status readback during a write is enabled,

the PEC values returned during the status readback operation

should be ignored. If status readback during a write is disabled,

the user can still use the normal readback operation to monitor

status register activity with PEC.

WATCHDOG TIMER

When enabled, an on-chip watchdog timer generates an alert

signal if 0x195 is not written to the software register within the

programmed timeout period. This feature is useful to ensure

that communication has not been lost between the MCU and

the AD5737 and that the datapath lines are working properly

(that is, SDIN, SCLK, and SYNC). If 0x195 is not received by

the software register within the timeout period, the ALERT pin

signals a fault condition. The ALERT pin is active high and can

be connected directly to the CLEAR pin to enable a clear in the

event that communication from the MCU is lost.

To enable the watchdog timer and set the timeout period (5 ms,

10 ms, 100 ms, or 200 ms), program the main control register

(see Table 20 and Table 21).

ALERT OUTPUT

The AD5737 is equipped with an ALERT pin. This pin is an

active high CMOS output. The AD5737 also has an internal

watchdog timer. When enabled, the watchdog timer monitors

SPI communications. If 0x195 is not received by the software

INTERNAL REFERENCE

The AD5737 contains an integrated 5 V voltage reference with

initial accuracy of ±5 mV maximum and a temperature coefficient

of ±10 ppm/°C maximum. The reference voltage is buffered and

is externally available for use elsewhere within the system.

EXTERNAL CURRENT SETTING RESISTOR

RSET is an internal sense resistor that is part of the voltage-to-

current conversion circuitry (see Figure 48). The stability of the

output current value over temperature is dependent on the stability

of the RSET value. To improve the stability of the output current

over temperature, the internal RSET resistor, R1, can be bypassed

and an external, 15 kΩ, low drift resistor can be connected to

the RSET_x pin of the AD5737. The external resistor is selected

via the DAC control register (see Table 23).

Table 1 provides the performance specifications for the AD5737

with both the internal RSET resistor and an external, 15 kΩ RSET

resistor. The use of an external RSET resistor allows for improved

performance over the internal RSET resistor option. The external

RSET resistor specifications assume an ideal resistor; the actual

performance depends on the absolute value and temperature

coefficient of the resistor used. This directly affects the gain error

of the output and, thus, the total unadjusted error. To arrive at

the gain/TUE error of the output with a specific external RSET

resistor, add the absolute error percentage of the RSET resistor

directly to the gain/TUE error of the AD5737 with the external

RSET resistor, as shown in Table 1 (expressed in % FSR).

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