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ADF4151 Datasheet(PDF) 1 Page - Analog Devices

Part # ADF4151
Description  Fractional-N/Integer-N PLL Synthesizer
PDF  28 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADF4151 Datasheet(HTML) 1 Page - Analog Devices

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Fractional-N/Integer-N PLL Synthesizer
Data Sheet
ADF4151
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
FEATURES
Fractional-N synthesizer and integer-N synthesizer
RF bandwidth to 3.5 GHz
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Separate charge pump supply (VP) allows extended tuning
voltage (up to 5.5 V) in 3 V systems
Programmable dual-modulus prescaler of 4/5 or 8/9
Programmable RF output phase
3-wire serial interface
Analog and digital lock detect
Switched bandwidth fast lock mode
Cycle slip reduction
APPLICATIONS
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMax, GSM,
PCS, DCS, DECT)
Test equipment
Wireless LANs, CATV equipment
Clock generation
GENERAL DESCRIPTION
The ADF4151 allows implementation of fractional-N or
integer-N phase-locked loop (PLL) frequency synthesizers
if used with an external voltage controlled oscillator (VCO),
loop filter, and external reference frequency.
The ADF4151 is used with external VCO parts and is footprint
and software compatible with the ADF4350. The part consists
of a low noise digital phase frequency detector (PFD), a precision
charge pump, and a programmable reference divider. There is
a Σ-Δ based fractional interpolator to allow programmable
fractional-N division. The INT, FRAC, and MOD registers
define an overall N divider [N = (INT + (FRAC/MOD))]. The
RF output phase is programmable for applications that require
a particular phase relationship between the output and the
reference. The ADF4151 also features cycle slip reduction
circuitry, leading to faster lock times without the need for
modifications to the loop filter.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V that can be powered down when not in use.
The ADF4151 is available in a 5 mm × 5 mm package.
FUNCTIONAL BLOCK DIAGRAM
MUXOUT
CPOUT
LD
SW
REFIN
CLK
DATA
LE
AVDDx
SDVDD
DVDD
VP
AGND
CE
CPGND
SDGND
DGND
RSET
RFIN+
RFIN–
PHASE
COMPARATOR
FLO SWITCH
CHARGE
PUMP
10-BIT R
COUNTER
÷2
DIVIDER
×2
DOUBLER
FUNCTION
LATCH
DATA REGISTER
INTEGER
REG
N COUNTER
FRACTION
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
MODULUS
REG
MULTIPLEXER
LOCK
DETECT
ADF4151
Figure 1.


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