ADF4151 datasheet(12/28 Pages) AD

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ADF4151

Data Sheet

Rev. B | Page 12 of 28

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4151 allows the user

to access various internal points on the chip. The state of

MUXOUT is controlled by M3, M2, and M1 (for details, see

Figure 21). Figure 17 shows the MUXOUT section in block

diagram form.

DGND

DVDD

CONTROL

MUX

MUXOUT

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

R COUNTER OUTPUT

N COUNTER OUTPUT

DGND

RESERVED

THREE-STATE-OUTPUT

DVDD

R COUNTER INPUT

Figure 17. MUXOUT Schematic

INPUT SHIFT REGISTERS

The ADF4151 digital section includes a 10-bit RF R counter,

a 16-bit RF N counter, a 12-bit FRAC counter, and a 12-bit

modulus counter. Data is clocked into the 32-bit shift register

on each rising edge of CLK. The data is clocked in MSB first.

Data is transferred from the shift register to one of six latches

on the rising edge of LE. The destination latch is determined

by the state of the three control bits (C3, C2, and C1) in the

shift register. There are three LSBs: DB2, DB1, and DB0, as

shown in Figure 2. The truth table for these bits is shown in

Table 5. Figure 18 shows a summary of how the latches are

programmed.

Table 5. C3, C2, and C1 Truth Table

Control Bits

PROGRAM MODES

Figure 19 through Figure 24 show how the program modes are

to be set up in the ADF4151.

A number of settings in the ADF4151 are double buffered.

These include the modulus value, phase value, R counter

value, reference doubler, reference divide-by-2, and current

setting. This means that two events must occur before the

part uses a new value of any of the double-buffered settings.

First, the new value is latched into the device by writing to the

appropriate register. Second, a new write must be performed

on Register R0. For example, any time the modulus value is

updated, Register R0 must be written to, thus ensuring that the

modulus value is loaded correctly.

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