DRV8834

www.ti.com

SLVSB19A – FEBRUARY 2012 – REVISED MARCH 2012

Table 1. TERMINAL FUNCTIONS

PIN

PIN

EXTERNAL COMPONENTS

NAME

DESCRIPTION

(PWP)

(RGE)

OR CONNECTIONS

POWER AND GROUND

21,

18,

Both the GND pin and device PowerPAD

GND

-

Device ground

PPAD

PPAD

must be connected to ground

Connect to motor supply. A 10-µF (minimum)

VM

18, 19

15, 16

-

Bridge A power supply

capacitor to GND is recommended.

Bypass to GND with 2.2-

μF (minimum), 6.3-V

capacitor. Can be used to provide logic high

VINT

20

17

-

Internal supply

voltage for configuration pins (except

nSLEEP).

May be connected to AVREF/BVREF inputs.

VREFO

24

21

O

Reference voltage output

Do not place a bypass capacitor on this pin.

Connect a 0.01-

μF, 16-V (minimum) X7R

VCP

17

14

O

High-side gate drive voltage

ceramic capacitor to VM.

CONTROL (Indexer Mode or Phase/Enable Mode)

Indexer mode: Logic low enables all outputs.

Phase/enable mode: Logic low enables the

nENBL/AENBL

10

7

I

Step motor enable/Bridge A enable

AOUTx outputs.

Internal pulldown.

Indexer mode: Rising edge moves indexer to

next step.

STEP/BENBL

11

8

I

Step input/Bridge B enable

Phase/enable mode: Logic low enables the

BOUTx outputs.

Internal pulldown.

Indexer mode: Level sets direction of step.

Phase/enable mode: Logic high sets BOUT1

DIR/BPHASE

12

9

I

Direction input/Bridge B Phase

high, BOUT2 low.

Internal pulldown.

Indexer mode: Controls microstep mode (full,

half, up to 1/32-step) along with M1.

M0/APHASE

13

10

I

Microstep mode/Bridge A phase

Phase/enable mode: Logic high sets AOUT1

high, AOUT2 low.

Internal pulldown.

Indexer mode: Controls microstep mode (full,

half, up to 1/32-step) along with M0.

M1

14

11

I

Microstep mode/Disable state

Phase/enable mode: Determines the state of

the outputs when xENBL = 0.

Internal pulldown.

Logic high to put the device in indexer mode.

Logic low to put the device into phase/enable

CONFIG

15

12

I

Device configuration

mode. State is latched at power-up and sleep

exit. Internal pulldown.

Logic high to enable device, logic low to

nSLEEP

1

22

I

Sleep mode input

enter low-power sleep mode and reset all

internal logic.

Reference voltage for winding current set.

Can be driven individually with an external

AVREF

22

19

I

Bridge A current set reference input

DACs for micro-stepping, or tied to a

reference voltage (e.g., VREFO).

Reference voltage for winding current set.

Can be driven individually with an external

BVREF

23

20

I

Bridge B current set reference input

DACs for micro-stepping, or tied to a

reference voltage (e.g., VREFO).

Determines decay mode for H-Bridge A (or A

ADECAY

3

24

I

Decay mode for bridge A

and B in indexer mode) – slow, fast or mixed

decay

Determines decay mode for H-Bridge B –

BDECAY

2

23

I

Decay mode for bridge B

slow, fast or mixed decay

(1)

Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output

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