DDC264

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SBAS368C

– MAY 2006 – REVISED JULY 2011

Configuration Register Bit Assignments

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

0

0

Clkdiv

0

0

Range[1]

Range[0]

Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Version

0

0

Reserved

0

0

0

Test

Bits 15:14

These bits must always be set to '0'.

Bit 13

Clkdiv

The Clkdiv input enables an internal divider on the system clock as shown in Table 10. When

Clkdiv = 1, the system clock is divided by 4. This configuration allows a system clock that is

faster by a factor of four, which in turn provides a finer quantization of the integration time,

because the CONV signal must be synchronized with the system clock for the best performance.

0 = Internal clock divider set to 1

1 = Internal clock divider set to 4

Table 10. Clkdiv Operation

Clkdiv Bit

CLK Divider Value

CLK Frequency

Internal Clock Frequency

0

1

5MHz

5MHz

1

4

20MHz

5MHz

Bits 12:11

These bits must always be set to '0'.

Bits 10:9

Range[1:0]

These bits set the full-scale range.

00 = Range 0 = 12.5pC

10 = Range 2 = 100.0pC

01 = Range 1 = 50.0pC

11 = Range 3 = 150.0pC

Bit 8

Format

Format selects how many bits are used in the data output word.

0 = 16-bit output

1 = 20-bit output

Bit 7

Version

This bit must be set to match the device being used.

Must be set to '0' for DDC264C.

Must be set to '1' for DDC264CK.

Bits 6:5

These bits must always be set to '0'.

Bit 4

Reserved

This bit is reserved and must be set to '0'.

Bits 3:1

These bits must always be set to '0'.

Bit 0

Test

When Test Mode is used, the inputs (IN1 through IN64) are disconnected from the DDC264

integrators to enable the user to measure a zero input signal regardless of the current supplied

to the inputs.

0 = TEST mode off

1 = TEST mode on

Copyright

© 2006–2011, Texas Instruments Incorporated

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