DDC264 datasheet(11/26 Pages) TI1

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12.5pF

25pF

VREF

Range[0] Bit

Range[1] Bit

RESET

REF2

ADC1A

INTA

REF1

IN1

ESD

Protection

Diodes

Input

Current

Integrator A

Integrator B

Photodiode

3pF

To Converter

INTB

QGND

Range Selection Capacitors (C )

DDC264

www.ti.com

SBAS368C

– MAY 2006 – REVISED JULY 2011

Basic Integration Cycle

At the completion of an A/D conversion, the charge

on the integration capacitor (CF) is reset with SREF1

The topology of the front end of the DDC264 is an

and SRESET (see Figure 21 and Figure 22a). This

analog integrator as shown in Figure 20. In this

process is done during reset. In this manner, the

diagram, only input IN1 is shown. The input stage

selected capacitor is charged to the reference

consists of an operational amplifier, a selectable

voltage, VREF. Once the integration capacitor is

feedback

capacitor

network

(CF),

and

several

charged, SREF1 and SRESET are switched so that

switches that implement the integration cycle. The

VREF is no longer connected to the amplifier circuit

timing relationships of all of the switches shown in

while it waits to begin integrating (see Figure 22b).

Figure 20 are illustrated in Figure 21. Figure 21

With the rising edge of CONV, SINTA closes, which

conceptualizes the operation of the integrator input

begins the integration of side A. This process puts the

stage of the DDC264 and should not be used as an

integrator

stage

into

its

integrate

mode

(see

exact timing tool for design.

Figure 22c).

See Figure 22 for the block diagrams of the reset,

Charge from the input signal is collected on the

integrate, wait, and convert states of the integrator

integration capacitor, causing the voltage output of

section of the DDC264. This internal switching

the amplifier to decrease. The falling edge of CONV

network is controlled externally with the convert pin

stops the integration by switching the input signal

(CONV) and the system clock (CLK). For the best

from side A to side B (SINTA and SINTB). Prior to the

noise performance, CONV must be synchronized with

falling edge of CONV, the signal on side B was

the falling edge of CLK. It is recommended that

converted by the A/D converter and reset during the

CONV toggle within

±10ns of the falling edge of CLK.

time that side A was integrating. With the falling edge

of CONV, side B starts integrating the input signal. At

The

noninverting

inputs

the

integrators

are

this point, the output voltage of the side A operational

connected to the QGND pin. Consequently, the

amplifier is presented to the input of the A/D

DDC264 analog ground, QGND, should be as clean

converter (see Figure 22d).

as possible. In Figure 20, the feedback capacitors

(CF) are shown in parallel between the inverting input

A special elecrostatic discharge (ESD) structure

and output of the operational amplifier. At the

protects the inputs but does not increase current

beginning of a conversion, the switches SA/D, SINTA,

leakage on the input pins.

SINTB, SREF1, SREF2, and SRESET are set (see

Figure 21).

Figure 20. Basic Integration Configuration

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