DLPR100

DLPS020 – DECEMBER 2009

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Status Register

Busy

Busy is a read only status register (S0) that is set to 1 state when the device is executing a write operation.

When write operation is completed the BUSY bit will be cleared to a 0 state indicating the device is ready for

further instructions.

Write Enable Latch (WEL)

Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing a Write

Enable Instruction. The WEL status bit is cleared to a 0 when the device is write disabled. A write disable state

occurs upon power-up.

Block Protect Bits (BP2, BP1, BP0)

Block Protect Bits are non-volatile read/write bits in the status register (S4,S3,S2) that provide Write Protection

control and status. Block Protect bits can be set using the Write Status Register instruction. The factory default

setting for the Block Protect bits is 0, none of the array protected. The Block Protect bits cannot be written to if

the Status Register Protect (SRP) bit is set to 1 and the Write Protect (/WP) pin is low.

Top/Bottom Block Protect (TB)

The Top/Bottom bit (TB) controls if the block protect bits (BP2,BP1,BP0) protect from the Top (TB=0) or the

Bottom (TB=1) of the array. Factory default setting is TB=0. The TB bit cannot be written to if the Status Register

Protect (SRP) bit is set to 1 and Write Protect (/WP) pin is low.

Reserved Bits

Status register bit location S6 is reserved for the future use. Device will read 0 for this bit.

Status Register Protect (SRP)

The Status Register Protect (SRP) bit is a read/write bit in status register (S7) that can be used in conjunction

with the Write Protect (WP) pin to disable writes to the status register. When the SRP bit is set to 0 state (factory

default) the WP pin has no control over Status Register. When the SRP bit is set to a 1 state, the Write Status

Register is locked out while the WP pin is low. When the WP pin is high the Write Status Register instruction is

allowed.

Table 1. Status Register Bit Locations

S7

S6

S5

S4

S3

S2

S1

S0

SRP

(R)

TB

BP2

BP1

BP0

WEL

BUSY

Table 2. Status Register Memory Protection

STATUS REGISTER

MEMORY PROTECTION

BP2

BP1

BP0

BLOCK(S)

ADDRESSES

DENSITY

PORTION

X

0

0

0

NONE

NONE

NONE

NONE

0

0

0

1

31

1F0000h-1FFFFFh

64KB

Upper 1/32

0

0

1

0

30 thru 31

1E0000h-1FFFFFh

128KB

Upper 1/16

0

0

1

1

28 thru 31

1C0000h-1FFFFFh

256KB

Upper 1/8

0

1

0

0

24 thru 31

180000h-1FFFFFh

512KB

Upper 1/4

0

1

0

1

16 thru 31

100000h-1FFFFFh

1MB

Upper 1/2

1

0

0

1

0

000000h-00FFFFh

64KB

Lower 1/32

1

0

1

0

0 and 1

000000h-01FFFFh

128KB

Lower 1/16

1

0

1

1

0 thru 3

000000h-03FFFFh

256KB

Lower 1/8

1

1

0

0

0 thru 7

000000h-07FFFFh

512KB

Lower 1/4

1

1

0

1

0 thru 15

000000h-0FFFFFh

1MB

Lower 1/2

(1)

x = don’t care

4

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