DLPR100

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DLPS020 – DECEMBER 2009

Table 2. Status Register Memory Protection (continued)

STATUS REGISTER

MEMORY PROTECTION

BP2

BP1

BP0

BLOCK(S)

ADDRESSES

DENSITY

PORTION

x

1

1

X

0 thru 31

000000h-1FFFFFh

2MB

ALL

Instructions

The instruction set of the DLPR100 consists of fifteen basic instructions that are fully controlled through the SPI

bus. Instructions are initiated by the falling edge of the Chip Select (CS). The first byte of data clocked into the

DIO input provides the instruction code. Data on the DIO input is sampled on the rising edge of the clock with

most significant bit (MSB) first. Instructions are completed with the rising edge of CS.

Table 3. Manufacturer and Device Identification

MANUFACTURER ID

(M7-M0)

Winbond Serial Flash

EFH

DEVICE ID

(ID7-ID0)

(ID15-ID0)

INSTRUCTION

ABh, 90h

9Fh

W25X16A

14h

3015h

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