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DLPR100 Datasheet(PDF) 9 Page - Texas Instruments |
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DLPR100 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 15 page  DLPR100 www.ti.com DLPS020 – DECEMBER 2009 AC ELECTRICAL CHARACTERISTICS (continued) VCC = 2.3 V to 3.6 V unless otherwise specified SYMBOL ALT DESCRIPTION MIN TYP MAX UNIT tCLH, tCLL Clock high, low time, for fast read(0Bh, 3Bh)/other instructions 6/7 ns except read data (03h)(1) tCLH, tCLL Clock high, low time, for all instructions 2.3 V-3.6 V VCC (1) 8 ns tCRLH, tCRLL Clock high, low time, for read data(03h) instructions(1) 8 ns tCLCH Clock rise time peak to peak(2) 0.1 V/ns tCHCL Clock fall time peak to peak(2) 0.1 V/ns tSLCH tCSS CS active setup time relative to CLK 5 ns tCHSL CS Not active Hold time relative to CLK 5 ns tDVCH tDSU Data in setup time 2 ns tCHDX tDH Data in hold time 5 ns tCHSH CS active hold time relative to CLK 5 ns tSHCH CS not active setup time relative to CLK 5 ns tSHSL tCSH CS deselect time (for array read->array read/erase or 50/100 ns program->Read Status Register) tSHQZ tDIS Output disable time(3) 7 ns tCLQV tV Clock low to output valid 2.7–3.6 V/ 3.0–3.6 V/ 2.3-3.6V 7/6/9 ns tCLQX tOH Output hold time 0 ns tHLCH HOLD active setup time relative to CLK 5 ns tCHHH HOLD active Hold time relative to CLK 5 ns tHHCH HOLD Not active setup time relative to CLK 5 ns tCHHL HOLD Not active Hold time relative to CLK 5 ns tHHQX tLZ HOLD to output low-Z(3) 7 ns tHLQZ tHZ HOLD to output high-Z (3) 12 ns tWHSL Write protect setup time before CS low(4) 20 ns tSHWL Write protect Hold time after CS high(4) 100 ns tDP CS high to power-down mode(3) 3 µs tRES1 CS high to standby mode without electronic signature Read(3) 3 µs tRES2 CS high to standby mode with electronic signature Read(3) 1.8 µs tW Write Status Register time 10 15 ms tBP1 Byte program time (first byte)(5) 30 50 µs tBP2 Additional byte program time (after first byte)(5) 6 12 µs tPP Page program time 1.6 3 ms tSE Sector erase time (4KB) 120 200 ms tBE Block erase time (64KB) 0.32 1 s tCE Chip erase time 10 20 s (1) Clock high + clock low must be less than or equal to 1/fC. (2) Value ensured by design and/or characterization, not production tested. (3) Value ensured by design and/or characterization, not production tested. (4) Only applicable as a constraint for Write Status Register instruction when Sector Protect Bit is set to 1. (5) For multiple bytes after the first byte within a page, tBPN = tBP1 + tBP2 * N(typical) and tBPN = tBP1 + tBP2 * N(max), where N = number of bytes programmed Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): DLPR100 |
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