GC6016 datasheet(21/46 Pages) TI1

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GC6016

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SLWS227A

– NOVEMBER 2010 – REVISED MARCH 2011

Any of the up to eight complex RX antenna/signal inputs across both sub-chips may be switched to one or more

of the up to 4 output streams of each sub-chip.

IF NCO

The NCO/mixer block generates in-phase and quadrature sinusoidal signals (cos/sin) and mixes them with the

switched antenna streams to frequency-translate the RX signals. The NCO contains a 48-bit frequency word and

48-bit accumulator.

BDC

The BDC supports the following modes and sample rates at its input (across both sub-chips):

•

Single

– 4 × DPD clock rate real, 2× DPD clock rate complex

•

Dual

– 2 × DPD clock rate real, DPD clock rate complex

•

Quad

– DPD clock rate real, 1/2 DPD clock rate complex

•

Octal

– 1/2 DPD clock rate real

Total decimation factors may be 1, 2, 4, 8, or 16. The decimation filtering is achieved with the cascade of the

real-to-complex filter (R2C), a fixed filter F1, and a fixed filter F2. The rejection of the F1 and F2 filters is:

•

Filter F1 (decimate by 1 or 2)

– If used, always followed by filter F2, so relaxed requirements

– 45% bandwidth, –107 dB stopband

•

Filter F2

– Recirculated 1–3 times to provide 2, 4, or 8× decimation factor

– 90% bandwidth, –75 dB, stop band

– 80% bandwidth, –106 dB, stop band

Equalizer

The receive equalizer is full-complex 16-tap filter that performs the following signal-processing functions:

•

Programmable spectral inversion at the input

•

Equalization of analog signal paths

•

Channel equalization for repeater applications

•

Gain/phase/fractional delay adjust (MIMO/smart antenna support)

•

Fixed dc offset compensation at the output

Independent complex coefficients for real and imaginary signal data allow full flexibility for independent

equalization of the direct- and cross-IQ signal components, as well as frequency-dependent IQ gain and phase

imbalance compensation. The programmable 16-bit coefficient sets (i.e., Cii, Cqq, Ciq and Cqi, for each tap) can be

updated on the fly.

IQ imbalance correction

Automatic correction of IQ imbalance is provided with a 1-tap blind adaptive algorithm. The correction coefficients

also may be programmed to fixed values. This block supports programmable integration intervals and flexible

gating of loop operation.

RX Distributor

The outputs from the RX sub-chips are routed to the RX distributor block, which enables arbitrary assignment of

RX streams to DDC channels and blocks.

RX Baseband Output Formatter

The RX baseband (BB) output formatter block accepts data from the DDC and formats the data for output on the

BB LVDS pins. A back-end AGC (beAGC) function is included that optionally adjusts the gain of each channel

and provides multiple format options. There are 12 unidirectional LVDS pairs for the RX BB interface.

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