ADC Data

ADC Clock

t

su

t

su

t

h

t

h

T0512-01

GC6016

SLWS227A

– NOVEMBER 2010 – REVISED MARCH 2011

www.ti.com

Table 17. General LVDS ADC Interface Table

Clock

ADC Type

Bits per Rail

ADC Format

ADC Input Timing Table

ADC Figure

Centered

ADS5400

1

Yes

W7

Table 18

Figure 19

ADS54RF63 (*)

1

No

W14

Table 19

Figure 19

ADS5463 (*)

1

No

W14

Table 19

Figure 19

ADS5474 (*)

1

No

W14

Table 19

Figure 19

RXA as baseband

2

Yes

Baseband format

– W14

Table 21

Figure 19

TX input

ADS61xx, ADS41xx,

2

Yes

B7

Table 20

Figure 19

ADS62pxx

ADS55xx

2

Yes

B7, W7

Table 20Table 18

Figure 19

ADS58B18

2

Yes

B7, W7

Table 20Table 18

Figure 19

ADS58B28,

2

Yes

B7, W7

Table 20Table 18

Figure 19

ADS62c1x

ADS64xx

6 or 7

Yes

W7

Table 18

Figure 20

ADS52xx

12 or 14

Yes

W7

Table 18

Figure 20

Table 18. RX ADC-W7 Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

RX input clock frequency, ADCA7 Clk

620

MHz

Input data setup time on port A before ADCA7

260

ps

Clk transition

Input data hold time on port A after ADCA7 Clk

170

ps

transition

Input data setup time on port B before ADCB7

260

ps

Clk transition

Input data hold time on port B after ADCB7 Clk

140

ps

transition

(1)

Chip specifications are production tested at 90

°C case temperature for the given specification. Early production lots are sample tested

at

–40°C.

(2)

Setup and hold times apply to data and appropriate ADC Clk, respectively. Timing is measured from ADC Clk threshold crossing.

Figure 19. RX ADC LVDS Timing Specifications (RXA and RXB)

34

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