SN74ACT2440

NuBus

™ INTERFACE CONTROLLER

SCHS010 – D3158, OCTOBER 1988 – REVISED JANUARY 1991

POST OFFICE BOX 655303

3

Terminal Functions

As previously explained, the input and output signals on the ’ACT2440 can be functionally organized into five

groups. The following tables briefly describe the controller signals in each group.

DATA/ADDRESS INTERFACE CONTROL SIGNALS

PIN

DESCRIPTION

NAME

NO.

DESCRIPTION

ACLK

3

Address clock. This output loads NuBus

™ address information onto the local board. During both master and slave start

cycles, this output changes on the sample edge (high-to-low) of the NuBus

™ clock signal (CLK).

A/D

66

Output select. This normally high output controls the multiplexing function of the address and data information onto

theNuBus

™. When low, address information is indicated. When high, data information is indicated. When the local boardis

the NuBus master, A/D goes low on the driving edge (low-to-high) of start and remains low for one NuBus

™ clock period.

Output enable. This active-low output enables data or address information onto the NuBus

™. ADEN is asserted on the driving

edge (low-to-highof the NuBus

™ clock signal (CLK) under any of the following conditions:

– The local board is the NuBus

™ master performing a write cycle and continuing until an acknowledge (ACK) is received

ADEN

65

from the NuBus

™.

– The local board is the NuBus

™ master performing a read cycle and continuing for one NuBus™ clock cycle.

– The local board is the selected NuBus

™ slave during an acknowledge cycle and the current cycle is a read.

AEN

4

Address enable. This active-low output signal enables address information onto the local board. When selected as a NuBus

™

slave, AEN goes low on the first sample edge after slave grant access (SGNTA) is asserted. AEN returns inactive on the first

sample edge after (SGNTA) returns inactive. If SGNTA is active (low) before the first sample edge after START, then address

information is placed onto the local board on the first sample edge after START.

DCLK

1

Data clock. This output loads NuBus

™ data onto the local board. This output changes on the sample edge (high-to-low) of

the NuBus

™ clock signal (CLK) under any of the following sets of comditions:

– The local board is the NuBus

™ master, the current cycle is a read, and an acknowledge (ACK) or interim acknowledge (TM0

during block transfers) has been received.

– The local board is a NuBus

™ slave, the current cycle is a write, and slave grant access (SGNTA) is asserted.

– The local board is a NuBus

™ slave, the current cycle is a block write. The first rising edge of DCLK will occur on the first

sample edge after SGNTA is taken active (low) and will remain high for two clock cycles. If SGNTA is active (low) during

the start cycle, DCLK will go active (high) on the first sample edge after START. The SIACK iinput controls the remaining

DCLK cycles with the exception of the last DCLK cycle. When the SIACK input is taken active (low), DCLK will go active

on the following sample edge. DCLK will remain high for one clock cycle and return low, regardless of the SIACK input. The

final DCLK cycle is controlled by the Local Acknowledge Input (LACK), as on normal write cycles.

DEN

2

Data Enable. The active-low output enables data to be placed onto the local board. DEN is asserted under either of the

following conditions:

g

– The local board is the NuBus

™ master performing a read cycle. (DEN goes low on the sample edge (high-to-low) of the

acknowledge cycle and remains low until the first sample edge after MHOLD returns inactive.) The local board is

the

selected NuBus

™ slave performing a write cycle. (DEN goes low on the first sample edge after slave grant access

(SGNTA) is asserted and remains low until the first sample edge after SGNTA returns inactive.)