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TPS767D301MPWPREP Datasheet(PDF) 4 Page - Texas Instruments |
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TPS767D301MPWPREP Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 21 page ![]() VI Vres See Note A. Vres t t t VO Threshold Voltage RESET Output 200-ms Delay 200-ms Delay Output Undefined Output Undefined VIT+ See Note B. VIT− VIT− VIT+ See Note B. Less than 5% of the output voltage TPS767D301-EP SGLS327A – FEBRUARY 2006 – REVISED APRIL 2010 www.ti.com TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. 1GND 3 Regulator 1 ground 1EN 4 I Regulator 1 enable 1IN 5, 6 I Regulator 1 input supply voltage 2GND 9 Regulator 2 ground 2EN 10 I Regulator 2 enable 2IN 11, 12 I Regulator 2 input supply voltage 2OUT 17, 18 O Regulator 2 output voltage 2RESET 22 O Regulator 2 reset 1OUT 23, 24 O Regulator 1 output voltage Regulator 1 output voltage feedback for adjustable version and no connect for fixed-output 1FB/NC 25 I version 1RESET 28 O Regulator 1 reset 1, 2, 7, 8, 13–16, NC No connection 19–21, 26, 27 TIMING DIAGRAM A. Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. B. VIT – Trip voltage typically is 5% lower than the output voltage (95% VO). 4 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated Product Folder Link(s): TPS767D301-EP |
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