TOIM5232

www.vishay.com

Vishay Semiconductors

Rev. 1.3, 04-Jul-12

11

Document Number: 81749

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

in figure 7 and figure 8. The difference is just the time scale.

It also indicates the delay of the decoded channel 2 vs.

channel 1.

Fig. 9 - Data reception with the setting 115.2 kbit/s

Channel 1 shows the signal from the transceiver. In this case

it is TFDU4101 with unsymmetrical switching times.

TFDU4101 is using tri-state outputs with push-pull drivers

with symmetrical pulse switching times. All Vishay IrDA

transceivers exhibit constant output pulse duration in SIR

mode of about 2 µs independent of the duration of the optical

input pulse.











“ECHO-ON” OR “ECHO-OFF” AND “LATENCY ALLOWANCE”

During transmission, the receiver inside a transceiver

package is exposed to very strong irradiance of the

transmitter, which causes overload conditions in the

receiver circuit. After transmission it takes some time to

recover from this condition and return to the specified

sensitivity.



During this time the receiver is in an unstable condition, and

at the output unexpected signals may arise. Also, during

transmission under overload conditions the receiver may

show signals on the RXD channel that are similar to or

identical with the transmitted signal. To get clean or at least

specified

conditions

for

the

receive

channel

during

transmission, different terms were defined. The time to allow

the receiver to recover from overload conditions is the

latency allowance or shorter, just the specified latency. This

is covered by the IrDA physical layer specification and is a

maximum of 10 ms. IrDA specifies shorter negotiable

latency. In SIR the minimum is 0.5 ms. This includes

software latency. Transceivers are in general below 0.3 ms.



In the first generations, some suppliers did not care for the

behavior of the RXD output of the transceivers during

transmission and latency time. The software is able to

handle that. The easiest way is to clean up the receiver

channel after sending the last pulse and waiting for the

latency period.



Later, many transceivers that block the RXD channel during

transmission and during the latency period were released to

the

market.

This

behavior

is

called

“Echo-off”.

Unfortunately, some OEMs like to use the signal from the

RXD channel during transmission, as a self-test feature for

testing the device on board without using the optical

domain. Therefore, many new devices have been developed

to echo the TXD input signal at the RXD output. Such

behavior is called “echo-on”.



Some software developed for “echo-off” applications is not

able to receive and understand the signals from echo-on

devices correctly.



Therefore, an add-on to the circuit shown in figure 1 was

generated to suppress the echo from the receiver during

transmission. This modification is shown in figure 10.



During transmission, the signal from the RXD output of the

transceiver is just gated by the transmit signal, (see the

oscilloscope picture in figure 11).

Fig. 10 - Demo Board Circuit with Echo-Suppression to be Used for Echo-On and Echo-Off Transceivers.

1->

2->

3->

21036

1) Ch1: TOIM4232; RD_IR, pin 15, vertical scale: 2 V/div.,

horizontal scale: 10 µs/div.

2) Ch2: TOIM4232; RD_232, pin 3

3) Ch3: TOIM4232; RD_LED, pin 10

TFDU4300:Vlog

Y1

C1

U2

TOIM4232*)

1

2

3

4

5

6

7

8

9

15

14

13

12

11

10

16

RESET

BR/D

RD_232

TD_232

Vcc_SD

X1

X2

GND

TD_LED

RD_IR

TD_IR

S2

S1

NC

RD_LED

Vcc

R3

+

C10

TXD

RXD

R5

U4

DG2039

1

4

8

3

7

2

6

5

NC_1

D

V+

INS2

INS1

COM_1

COM_2

NO_2

C8

DTR (RESET)

Vcc

+C2

External input

3.6V max.

U1

MAX3232

13

8

11

10

1

3

5

2

6

12

9

14

7

16

15

R1IN

R2IN

T1IN

T2IN

C+

C1-

C2+

C2-

V+

V-

R1OUT

R2OUT

T1OUT

T2OUT

VCC

optional

+

U3

TFDU4101

2

4

6

8

5

3

1

7

Cathode

RXD

Vcc1

GND

SD

TXD

Anode

.

This line not used forTFDU4101

C6

+

R2

C3

J2

CON2

1

2

Z2

C7

+

+

C11

J1

CON9

1

2

3

4

5

6

7

8

9

Pin7: TFDU4101:NC

RTS (BR/D)

TFDU4301

C5

C4

C9

Z1

R1

+

R4

*) For TOIM5232 pinning, see figure 1.

21047