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WM8311 Datasheet(PDF) 40 Page - Wolfson Microelectronics plc

Part # WM8311
Description  Processor Power Management Subsystem
PDF  302 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8311 Datasheet(HTML) 40 Page - Wolfson Microelectronics plc

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WM8311
Pre-Production
w
PP, May 2012, Rev 3.1
40
GPIO OFF request
Requires a GPIO to be configured as “Power
On/Off request”. See Section 21.
OFF_GPIO
Power Sequence failure
DC-DC converters, LDOs or CLKOUT circuits
(including FLL) have failed to start up within the
permitted time.
OFF_PWR_SEQ
Internal LDO error
Error condition detected in LDO13
OFF_INTLDO_ERR
SLEEP
Software SLEEP request
Writing CHIP_SLP = 1. See Table 2.
See note 4 and note 5
GPIO SLEEP request
Requires a GPIO to be configured as “Sleep
request” or “Sleep/Wake request”. See
Section 21.
See note 4 and note 5
Table 3 Power State Transition Events
Notes:
1.
An ON sequence is only permitted when the supply voltage SYSVDD exceeds a programmable threshold VSYSOK. See
Section 24.4 for details of SYSVDD voltage monitoring.
2.
Selected OFF events may be masked during Battery Charging using the CHG_OFF_MASK bit. This allows user-initiated OFF
events (Software OFF, ON pin request, GPIO OFF request) to be inhibited. See Section 17.7.2.
3.
These Reset conditions result in an OFF transition followed by an ON transition. These events are recorded as Reset events in
the ‘ON Source’ register.
4.
SLEEP transitions are not possible when any of the Battery Charger Interrupts is set. If any of the Battery Charger Interrupts is
asserted when a SLEEP transition is requested, then the transition will be unsuccessful and the WM8311 will remain in the ON
power state. See Section 17.7.8 for details of the Battery Charger Interrupts.
5.
SLEEP events are not recorded in the ‘OFF Source’ register.
11.4 POWER STATE INTERRUPTS
Power State transitions are associated with a number of Interrupt event flags. Transitions to
BACKUP, SLEEP, ON or OFF states are indicated by the Interrupt bits described in Table 4. Each of
these secondary interrupts triggers a primary Power State Interrupt, PS_INT (see Section 23). This
can be masked by setting the mask bit(s) as described in Table 4.
ADDRESS
BIT
LABEL
DESCRIPTION
R16402
(4012h)
Interrupt Status
2
2
PS_POR_EINT
Power On Reset interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
1
PS_SLEEP_OFF_EINT
SLEEP or OFF interrupt (Power state
transition to SLEEP or OFF states)
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
0
PS_ON_WAKE_EINT
ON or WAKE interrupt (Power state
transition to ON state)
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
R16410
(401Ah)
Interrupt Status
2 Mask
2
IM_PS_POR_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
1
IM_PS_SLEEP_OFF_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
0
IM_PS_ON_WAKE_EINT
Interrupt mask.
0 = Do not mask interrupt.



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