WM8311 datasheet(43/302 Pages) WOLFSON

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Pre-Production

WM8311

PP, May 2012, Rev 3.1

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

RST_SLPENA

Sets the output status of RESET

¯¯¯¯¯¯ pin

in SLEEP

0 = RESET

¯¯¯¯¯¯ high (not asserted)

1 = RESET

¯¯¯¯¯¯ low (asserted)

Protected by user key

1:0

RST_DUR

Delay period for releasing RESET

¯¯¯¯¯¯

after ON or WAKE sequence

00 = 3ms

01 = 11ms

10 = 51ms

11 = 101ms

Protected by user key

Table 7 RESET Pin Control Registers

The WM8311 can generate an Auxiliary Reset output via a GPIO pin configured as “Auxiliary Reset”

output (see Section 21). This signal is asserted in the OFF state. The status of the Auxiliary Reset in

the SLEEP state is configurable, using the AUXRST_SLPENA register bit as defined in Table 8.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R16390 (4006h)

Reset Control

AUXRST_SLPE

Sets the output status of Auxiliary

Reset (GPIO) function in SLEEP

0 = Auxiliary Reset not asserted

1 = Auxiliary Reset asserted

Protected by user key

Table 8 Auxiliary Reset (GPIO) Control

The timing details of the RESET

¯¯¯¯¯¯ pin relative to an ON state transition are illustrated in Figure 6.

Power State

Time

RESET pin

OFF

State Transition

Time delay set by

PWRSTATE_DELAY

1ms or 10ms

ON transition.

Nominal duration = 5 x 2ms

RESET delay set by RST_DUR

3ms, 11ms, 51ms or 101ms

Figure 6 RESET Pin Output

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