WM8311 datasheet(169/302 Pages) WOLFSON

169 / 302 page

Pre-Production

WM8311

PP, May 2012, Rev 3.1

169

The SYSLO status can be read from the SYSLO_STS register bit. This bit is asserted when SYSVDD

is below the SYSLO threshold.

The WM8311 can also indicate the status of the SYSOK signal via a GPIO pin configured as a

“SYSVDD Good” output (see Section 21). A GPIO pin configured as “SYSVDD Good” output will be

asserted when the SYSVDD is above the SYSOK threshold.

VSYSOK

VSYSVDD

time

VSYSLO

VSHUTDOWN

SYSOK (SYSLO)

SHUTDOWN

time

Figure 39 SYSVDD Monitoring

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R16385

(4001h)

SYSVDD

Control

15:14

SYSLO_ERR_

ACT

SYSLO Error Action

Selects the action taken when SYSLO is

asserted

00 = Interrupt

01 = WAKE transition

10 = Reserved

11 = OFF transition

SYSLO_STS

SYSLO Status

0 = Normal

1 = SYSVDD is below SYSLO threshold

6:4

SYSLO_THR

[2:0]

010

SYSLO threshold (falling SYSVDD)

This is the falling SYSVDD voltage at

which SYSLO will be asserted

000 = 2.8V

001 = 2.9V

…

111 = 3.5V

2:0

SYSOK_THR

[2:0]

101

SYSOK threshold (rising SYSVDD)

This is the rising SYSVDD voltage at

which SYSOK will be asserted

000 = 2.8V

001 = 2.9V

…

111 = 3.5V

Note that the SYSOK hysteresis margin is

added to these threshold levels.

Table 108 SYSVDD Monitoring Control

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