AD9915BCPZ datasheet(35/48 Pages) AD

35 / 48 page

Data Sheet

AD9915

Rev. A | Page 35 of 48

The synchronization mechanism begins with the clock

distribution and delay equalization block, which is used to

ensure that all devices receive an edge-aligned REF_CLK signal.

However, even though the REF_CLK signal is edge aligned

among all devices, this alone does not guarantee that the clock

state of each internal clock generator is coordinated with the

others. This is the role of the synchronization redistribution

circuit, which accepts the SYNC_OUT signal generated by the

master device and redistributes it to the SYNC_IN input of the

slave units (as well as feeding it back to the master). The goal of

the redistributed SYNC_OUT signal from the master device is

to deliver an edge-aligned SYNC_IN signal to all of the sync

receivers. Assuming that all devices share the same REF_CLK

edge (due to the clock distribution and delay equalization

block) and all devices share the same SYNC_IN edge (due to

the synchronization distribution and delay equalization block),

all devices should generate an internal sync pulse in unison and

the synchronized sync pulses cause all of the devices to assume

the same predefined clock state simultaneously; that is, the

internal clocks of all devices become fully synchronized. The

synchronization mechanism depends on the reliable generation

of a sync pulse by the edge detection block in the sync receiver.

Generation of a valid sync pulse, however, requires proper

sampling of the rising edge of the SYNC_IN signal with the

rising edge of the local SYSCLK. If the edge timing of these

signals fails to meet the setup or hold time requirements of the

internal latches in the edge detection circuitry, the proper

generation of the sync pulse is in jeopardy.

Ambient operating temperature and self-heating of the AD9915

must also be considered when attempting to synchronize

multiple devices. In general, the propagation delay from the

SYNC_IN pin to the internal clock generators is fixed for a

given operating temperature. However, large temperature

differences between devices or rapid increases in device

temperature at power-up increase the complexity of

synchronization.

Table 14 and Table 15 display the delay time increment for both

SYNC_IN and SYNC_OUT vs. their corresponding register

values, from 0 to 7.

Table 14. SYNC_IN Delay (Total Delay = 1.2 ns)

Delay Step

Increment, Typ (ns)

0 to 1

0.26

1 to 2

0.15

2 to 3

0.15

3 to 4

0.15

4 to 5

0.15

5 to 6

0.17

6 to 7

0.17

Table 15. SYNC_OUT Delay (Total Delay = 1.97 ns)

Delay Step

Increment, Typ (ns)

0 to 1

0.17

1 to 2

0.3

2 to 3

0.3

3 to 4

0.3

4 to 5

0.3

5 to 6

0.3

6 to 7

0.3

Figure 49. Configuration of Multiple Devices to Be Synchronized

SYNC

OUT

REF_CLK

AD9915

NUMBER 1

MASTER DEVICE

FPGA

DATA

FPGA

DATA

FPGA

DATA

EDGE

ALIGNED

AT REF_CLK

INPUTS

EDGE

ALIGNED

AT SYNC_IN

INPUTS

SYNC

OUT

REF_CLK

AD9915

NUMBER 2

SYNC

OUT

REF_CLK

AD9915

NUMBER 3

(FOR EXAMPLE AD951x)

CLOCK DISTRIBUTION

AND

DELAY EQUALIZATION

SYNCHRONIZATION

DISTRIBUTION AND

DELAY EQUALIZATION

(FOR EXAMPLE AD951x)

CLOCK

SOURCE

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