AD5011

–7–

REV PrA

PRELIMINARY TECHNICAL DATA

Control Register Functions

Mnemonic

Function

R/

W

When R/

W is high, the register bank addressed by SEL[2:0] is loaded into the output shift register.

Serial data will subsequently be output onto the DR pin.

If R/

W is low, the serial input data located

at D[11:0] will be written into the register bank addressed by SEL[2:0].

PWDN-Tx

When

PWDN-Tx is low, the entire transmit channel is powered down. The line driver output is

high impedance when the transmit channel is powered down.

PWDN-Rx

When this bit is low, the entire receive channel is powered down.

LOOPBACK

When this bit is high, analog loopback is selected.

AA-BUF-BP

When this bit equals 1, the ADC buffer is bypassed.

AA-FLTR-BP

When this bit equals 1, the receive filter is bypassed.

Tx-GAIN-SEL

When Tx-GAIN-SEL equals 1, the output of the transmit filter is attenuated by 6 dB.

WRBOTH

The transmit and receive programmable filter corner frequencies are addressed by the 11-bits words

TPFD and RPFD respectively.

TPFD data is loaded from the serial input register to the transmit

filter register if SEL[2:0] = 010.

RPFD data is written to the receive filter register if SEL[2:0] =

010.

If WRBOTH equals 1 during either of the above conditions, the word in the serial input

register is loaded into both the TFPD and RFPD registers.

Table 1. Control Register

Serial Register SEL[2:0]=000

SEL[2:0]=001

SEL[2:0]=010

SEL[2:0]=011

Control Reg

Tx Prog Filt Reg

Rx Prog Filt Reg

Test Purposes Only

D[15]

R/

W = 0

R/

W = 0

R/

W = 0

R/

W = 0

D[14]

SEL[2] = 0

SEL[2] = 0

SEL[2] = 0

SEL[2] = 0

D[13]

SEL[1] = 0

SEL[1] = 0

SEL[1] = 1

SEL[1] = 1

D[12]

SEL[0] = 0

SEL[0] = 1

SEL[0] = 0

SEL[0] = 1

D[11]

PWDN-Tx

WRBOTH

WRBOTH

Reserved

D[10]

PWDN-Rx

TPFD[10]

RPFD[10]

Reserved

D[9]

LOOPBACK

TPFD[9]

RPFD[9]

Reserved

D[8]

AA-BUF-BP

TFPD[8]

RPFD[8]

Reserved

D[7]

AA-FLTR-BP

TFPD[7]

RFPD[7]

Reserved

D[6]

Tx-GAIN-SEL

TFPD[6]

RFPD[6]

Reserved

D[5]

Tx-DACOUT

TFPD[5]

RFPD[5]

Reserved

D[4]

Tx-LPF-BP

TFPD[4]

RFPD[4]

Reserved

D[3]

Tx-DRVR-BP

TFPD[3]

RFPD[3]

Reserved

D[2]

PGA-GC2

TFPD[2]

RFPD[2]

Reserved

D[1]

PGA-GC1

TFPD[1]

RFPD[1]

Reserved

D[0]

PGA-GC0

TFPD[0]

RFPD[0]

Reserved

Configuring the Transmit Channel

Tx-DACOUT Tx-FILT-BP

Tx-DRVR-BP

Configuration

0

0

0

Default.

All Components in the Tx channel are used.

1

0

0

The DAC output is seen at the line driver output pins.

The line driver

amplifier output is in a high impedance state.

0

1

0

The Tx filter is bypassed.

The DACOUT is fed to the PGA.

The

filter amplifier output is in a high impedance state.

0

0

1

The filter output is seen at the line driver output pins.

The line driver

amplifier output is in a high impedance state.