AD5011 datasheet(3/8 Pages) AD

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AD5011

–3–

REV PrA

PRELIMINARY TECHNICAL DATA

Parameter

AD7346B

Units

Test Conditions/Comments

Min

Typ

Max

LOGICOUTPUTS

Output Logic High, VOH

VDD - 0.3

IOUT = 200 mA

Output Logic Low, VOL

0.3

IOUT = 200 mA

POWER SUPPLIES

AVDD, DVDD

3.15

3.3

3.45

IDD

Normal Mode (excluding Driver)

Line Driver

33 W Differential Load

1Operating temperature range is as follows: B Version: –40°C to +85°C.

2The complete transmit path spectrum and pulse shape comply with ETSI requirements. SNR and THD are measured within a 547 kHz bandwidth. Noise and Spurious

tones beyong 540 kHz are therefore excluded.

3The transmit DAC maximum update rate is half the maximum output data rate i.e. 1168 kHz. The maximum transmit clock is 16 x 1168 = 18.688 MHz.

4There are three ranges (bottom range, mid range, top range), each range being divided into eight steps. The transmit filter corner frequency can be set independently from

the receive filter corner frequency. the filter tuning circuit requires a continuous 16.384 MHz clock applied to the Fclk pin.

5Transformer turns ratio = 1:2:3 at 50 kHz when loaded by ETSI (RTR/TM3036) HDSL test loops.

6With 547 kHz filter snd 0 dB PGA gain selected.

7The PGA gain is set by setting the PGA-GC bits in the control register.

8The input switching threshold voltage is approximately 1.2 V to allow interfacing to 2.5 V and 3.3 V logic.

9The output level is determined by the voltage on the logic supply pin V

DRIVE.

Specifications subject to change without notice.

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