AD5011

–4–

REV PrA

PRELIMINARY TECHNICAL DATA

Limit at

Parameter

(B Version)

Units

Test Conditions/Comments

ADCCLK <= 1160kHz

ns min

ADCCLK Rising Edge to SCLK Rising Edge Delay

ns typ

ns min

SCLK Rising Edge to ADCCLK Falling Edge Delay

ns typ

26.939

ns min

SCLK Period (1/32*ADCCLK Period)

5

ns min

Data Setup Time Before SCLK Falling Edge

10

ns min

Data Hold Time After SCLK Falling Edge

1160 kHz < ADCCLK <= 2320 kHz

20

ns min

ADCCLK Rising Edge to SCLK Rising Edge Delay

ns typ

1.5*t8

ns min

SCLK Rising Edge to ADCCLK Falling Edge Delay

ns typ

26.939

ns min

SCLK Period (1/16*ADCCLK Period)

5

ns min

Data Setup Time Before SCLK Falling Edge

10

ns min

Data Hold Time After SCLK Falling Edge

TRANSMIT DAC

53.5

ns min

TxCLK Period (1/18.688 MHz)

12

ns min

Data Setup Time Before TxCLK Rising Edge

10

ns min

Data Hold Time After TxCLK Rising Edge

ns min

TxSYNC Low Time

3

ns min

TxCLK Rising Edge to TxSYNC Falling Edge Delay

t11/2

ns max

CONTROL REGISTER

50

ns min

SPICLK Period

76

ns typ

15

ns min

TFS Setup Time Before SPICLK Falling Edge

ns max

15

ns min

TFS Hold Time After SPICLK Falling Edge

ns max

ns typ

TFS High Time

7

ns min

DT Setup Time Before SPICLK Falling Edge

10

ns min

DT Hold Time After SPICLK Falling Edge

7

ns min

DR Setup Time Before SPICLK Falling Edge (R/

W = 1)

10

ns min

DR Hold Time After SPICLK Falling Edge (R/

W = 1)

Guaranteed by design but not production tested.

D1 1

D1 0

D 1

D0

AD C CL K

D1 1

D 1 0

D9

SCL K

SDO

t

3

Figure 1. ADC Timing (ADCCLK <= 1160 kHz)

SCLK activity and serial output data activity does not coincide with the sesitive ADCCLK clock edges