AD7304 datasheet(6/14 Pages) AD

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AD7304/AD7305

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REV. A

AD7304 PIN FUNCTION DESCRIPTIONS

Pin #

Name

Function

1VOUTB

Channel B rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REFB pin. Output

is open circuit when SHDN is enabled.

2VOUTA

Channel A rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REFA pin. Output

is open circuit when SHDN is enabled.

3VSS

Negative Power Supply Input. Specified range of operation 0 V to –5.5 V.

4VREFA

Channel A Reference Input. Establishes VOUTA full-scale voltage. Specified range of operation VSS < VREFA < VDD.

5VREFB

Channel B Reference Input. Establishes VOUTB full-scale voltage. Specified range of operation VSS < VREFB < VDD.

GND

Common Analog and Digital Ground.

LDAC

Load DAC register strobe, active low. Transfers all four Input Register data into their DAC registers. Asynchronous

active low input. DAC Register is transparent when LDAC = 0. See Control Logic Truth Table for operation.

CLR

Clears all Input and DAC registers to the zero condition. Asynchronous active low input. The serial register is not effected .

Chip Select, Active Low Input. Disables shift register loading when high. Transfers Serial Input Register Data to the

decoded Input Register when CS returns HIGH. Does not effect LDAC operation.

CLK

Clock input, positive edge clocks data into shift register. Disabled by chip select CS.

SDI/SHDN

Serial Data-Input loads directly into the shift register, MSB first. Hardware shutdown (SHDN) control input, active

when pin is left floating by a three-state logic driver. Does not effect DAC register contents as long as power is

present on VDD.

VREFD

Channel D Reference Input. Establishes VOUTD full-scale voltage. Specified range of operation VSS < VREFD < VDD.

VREFC

Channel C Reference Input. Establishes VOUTC full-scale voltage. Specified range of operation VSS < VREFC < VDD.

VDD

Positive power supply input. Specified range of operation +2.7 V to +5.5 V.

VOUTD

Channel D rail-to-rail buffered DAC voltage output. Full-scale set by reference voltage applied to V REFD pin. Output

is open circuit when SHDN is enabled.

VOUTC

Channel C rail-to-rail buffered DAC voltage output. Full-scale set by reference voltage applied to V REFC pin. Output

is open circuit when SHDN is enabled.

AD7305 PIN FUNCTION DESCRIPTIONS

Pin #

Name

Function

1VOUTB

Channel B rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REFB pin. Output

is open circuit when SHDN is enabled.

2VOUTA

Channel A rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REFA pin. Output

is open circuit when SHDN is enabled.

3VSS

Negative Power Supply Input. Specified range of operation 0 V to –5.5 V.

4VREF

Channel B Reference Input. Establishes VOUT full-scale voltage. Specified range of operation VSS < VREF < VDD.

GND

Common Analog and Digital Ground.

LDAC

Load DAC register strobe, active low. Transfers all four Input Register data into their DAC registers. Asynchronous

active low input. DAC Register is transparent when LDAC = 0. See Control Logic Truth Table for operation.

DB7

MSB Digital Input Data Bit.

DB6

Data Bit 6.

DB5

Data Bit 5.

DB4

Data Bit 4.

DB3

Data Bit 3.

DB2

Data Bit 2.

DB1

Data Bit 1.

DB0

LSB Digital Input Data Bit.

Write data into Input Register control line, active low. See Control Logic Truth Table for operation.

Address Bit 1.

A0/SHDN

Address Bit 0/Hardware shutdown (SHDN) control input, active when pin is left floating by a three-state logic driver.

Does not effect DAC register contents as long as power is present on VDD.

VDD

Positive Power Supply Input. Specified range of operation +2.7 V to +5.5 V.

VOUTD

Channel D rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REFD pin. Output

is open circuit when SHDN is enabled.

VOUTC

Channel C rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to VREFC pin. Output

is open circuit when SHDN is enabled.

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