AD7304/AD7305

–12–

REV. A

AD7304

INPUT

REGISTER

R

DAC A

OE

DAC A

REGISTER

R

INPUT

REGISTER

R

DAC B

OE

DAC C

REGISTER

R

DAC B

REGISTER

R

INPUT

REGISTER

R

DAC C

OE

DAC D

REGISTER

R

DACA

B

C

D

2:4

DECODE

A0

A1

SDC

SAC

D0

D1

D2

D3

D4

D5

D6

D7

8

EN

320k

280k

80k

640k

680k

LDAC

CS

SDI

DQ

g

DQ

g

DQ

g

DQ

g

INPUT

REGISTER

R

POWER-

ON

RESET

CLR

GND

CLK

DAC D

OE

Figure 31. AD7304 Equivalent Logic Interface

AD7304 Hardware Shutdown SHDN

If a three-state driver is used on the SDI/SHDN pin, the AD7304

can be placed into a power shutdown mode when the SDI/

SHDN pin is placed in a high impedance state. For proper

operation no other termination voltages should be present on

this pin. An internal window comparator will detect when the

logic voltage on the SHDN pin is between 28% and 36% of

voltage on the SHDN pin. The four DAC output voltages be-

come high impedance with a nominal resistance of 120 k

Ω to

ground. See Figure 30 for an equivalent circuit.

AD7304/AD7305 POWER ON RESET

strobe forces all the Input and DAC registers to the zero-code

creasing ramp in order to have consistent results, especially in

on the power ON reset performance. The DAC register data

will stay at zero until a valid serial register software load takes

place. In the case of the double buffered AD7305 the output

DAC register can only be changed once the LDAC strobe is

initiated.

AD7305 PARALLEL DATA INTERFACE

The AD7305 has an 8-bit parallel interface DB7 = MSB,

DB0 = LSB. Two address Bits A1 and A0 are decoded when an

active low write strobe is placed on the WR pin, see Table III.

The WR is a level-sensitive input pin, therefore the data setup

and data hold times defined in the TIMING SPECIFICATIONS

need to be adhered to.

The LDAC pin provides the capability of simultaneously updat-

ing all DAC registers with new data from the Input Registers at

the same time. This will result in the analog outputs all chang-

ing to their new values at the same time. The LDAC pin is a

level-sensitive input. If the simultaneous update feature is not

required the LDAC pin can be tied to logic low. When the

LDAC is tied to logic low, the DAC Registers become transpar-

ent and the Input Register data determines the DAC output

voltage. See Figure 32 for an equivalent interface logic diagram.

AD7226 Pin Compatibility

By tying the LDAC pin to ground, the AD7305 has the same

pin out and functionality as the AD7226, with the exception of

a lower power supply operating voltage.

AD7305 Hardware Shutdown SHDN

If a three state driver is used on the A0/SHDN pin, the AD7305

can be placed into a power shutdown mode when the A0/SHDN

pin is placed in a high impedance state. For proper operation no

other termination voltages should be present on this pin. An

internal window comparator will detect when the logic voltage

impedance internal bias generator provides this voltage on the

SHDN pin. The four DAC output voltages become high imped-

ance with a nominal resistance of 120 k

Ω to ground.

ESD Protection Circuits

All logic input pins contain back-biased ESD protection Zeners

Figure 33).

GND

DIGITAL

INPUTS

Figure 33. Equivalent ESD Protection Circuits

AD7305

INPUT

REGISTER

R

DAC A

OE

DAC A

REGISTER

R

INPUT

REGISTER

R

DAC B

OE

DAC C

REGISTER

R

DAC B

REGISTER

R

INPUT

REGISTER

R

DAC C

OE

DAC D

REGISTER

R

DAC A

B

C

D

2:4

DECODE

8

320k

280k

80k

640k

680k

LDAC

WR

INPUT

REGISTER

R

POWER-

ON

RESET

GND

DATA

DB0–DB7

DAC D

OE

A1

A0/SHDN

Figure 32. AD7305 Equivalent Logic Interface