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Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).

It is assumed that the command byte has previously been set to ‘00’ (read input port register).

Fig 10. Read input port register (input latch disabled), scenario 1

1

0

0

A2 A1 A0

1

A

S0

START condition

R/W

acknowledge

from slave

002aah375

A

SCL

SDA

A

read from port 0

P

9

8

7

6

5

4

3

2

1

I0.x

slave address

STOP condition

acknowledge

from master

A

I1.x

acknowledge

from master

A

I0.x

acknowledge

from master

1

I1.x

non acknowledge

from master

data into port 0

read from port 1

data into port 1

INT

6543210

7

6543210

7

6543210

7

6543210

7

INT