PCAL9535APW datasheet(14/46 Pages) NXP

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PCAL9535A

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Product data sheet

Rev. 1 — 28 September 2012

14 of 46

NXP Semiconductors

PCAL9535A

Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O

6.5 Interrupt output

An interrupt is generated by any rising or falling edge of the port inputs in the Input mode.

After time tv(INT), the signal INT is valid. The interrupt is reset when data on the port

changes back to the original value or when data is read form the port that generated the

interrupt (see Figure 10). Resetting occurs in the Read mode at the acknowledge (ACK)

or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that

occur during the ACK or NACK clock pulse can be lost (or be very short) due to the

resetting of the interrupt during this pulse. Any change of the I/Os after resetting is

detected and is transmitted as INT.

A pin configured as an output cannot cause an interrupt. Changing an I/O from an output

to an input may cause a false interrupt to occur, if the state of the pin does not match the

contents of the Input Port register.

The INT output has an open-drain structure and requires pull-up resistor to VDD.

When using the input latch feature, the input pin state is latched. The interrupt is reset only

when data is read from the port that generated the interrupt. The reset occurs in the Read

mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of

the SCL signal.

Bus transactions

The PCAL9535A is an I2C-bus slave device. Data is exchanged between the master and

PCAL9535A through write and read commands using I2C-bus. The two communication

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

7.1 Writing to the port registers

Data is transmitted to the PCAL9535A by sending the device address and setting the least

significant bit to a logic 0 (see Figure 4 “PCAL9535A device address”). The command

byte is sent after the address and determines which register will receive the data following

the command byte.

Twenty-two registers within the PCAL9535A are configured to operate as eleven register

pairs. The eleven pairs are input port, output port, polarity inversion, configuration,

output drive strength (two 16-bit registers), input latch, pull-up/pull-down enable,

pull-up/pull-down selection, interrupt mask, and interrupt status registers. After sending

data to one register, the next data byte is sent to the other register in the pair (see Figure 7

and Figure 8). For example, if the first byte is sent to Output Port 1 (register 3), the next

byte is stored in Output Port 0 (register 2).

There is no limitation on the number of data bytes sent in one write transmission. In this

way, the host can continuously update a register pair independently of the other registers,

or the host can simply update a single register.

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