AD7705 datasheet(15/32 Pages) AD

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AD7705/AD7706

–15–

REV. A

CIRCUIT DESCRIPTION

The AD7705/AD7706 is a sigma-delta A/D converter with on-

chip digital filtering, intended for the measurement of wide

dynamic range, low frequency signals such as those in industrial

control or process control applications. It contains a sigma-delta

(or charge-balancing) ADC, a calibration microcontroller with

on-chip static RAM, a clock oscillator, a digital filter and a bi-

directional serial communications port. The part consumes only

320

µA of power supply current, making it ideal for battery-

powered or loop-powered instruments. These parts operate with

a supply voltage of 2.7 V to 3.3 V or 4.75 V to 5.25 V.

The AD7705 contains two programmable-gain fully differential

analog input channels, while the AD7706 contains three pseudo

differential analog input channels. The selectable gains on these

inputs are 1, 2, 4, 8, 16, 32, 64 and 128 allowing the part to

accept unipolar signals of between 0 mV to +20 mV and 0 V to

+2.5 V, or bipolar signals in the range from

±20 mV to ±2.5 V

when the reference input voltage equals +2.5 V. With a refer-

ence voltage of +1.225 V, the input ranges are from 0 mV to

+10 mV to 0 V to +1.225 V in unipolar mode, and from

±10 mV

±1.225 V in bipolar mode. Note that the bipolar ranges are

with respect to AIN(–) on the AD7705, and with respect to

COMMON on the AD7706, and not with respect to GND.

The input signal to the analog input is continuously sampled

at a rate determined by the frequency of the master clock,

MCLK IN, and the selected gain. A charge-balancing A/D

converter (Sigma-Delta Modulator) converts the sampled signal

into a digital pulse train whose duty cycle contains the digital

information. The programmable gain function on the analog

input is also incorporated in this sigma-delta modulator with the

input sampling frequency being modified to give the higher

gains. A sinc

3 digital low-pass filter processes the output of the

sigma-delta modulator and updates the output register at a rate

determined by the first notch frequency of this filter. The out-

put data can be read from the serial port randomly or periodi-

cally at any rate up to the output register update rate. The first

notch of this digital filter (and hence its –3 dB frequency) can

be programmed via the Setup Register bits FS0 and FS1. With

a master clock frequency of 2.4576 MHz, the programmable

range for this first notch frequency is from 50 Hz to 500 Hz,

giving a programmable range for the –3 dB frequency of

13.1 Hz to 131 Hz. With a master clock frequency of 1 MHz,

the programmable range for this first notch frequency is from

20 Hz to 200 Hz, giving a programmable range for the –3 dB

frequency of 5.24 Hz to 52.4 Hz.

The basic connection diagram for the AD7705 is shown in

Figure 10. This shows the AD7705 being driven from the ana-

log +5 V supply. An AD780, precision +2.5 V reference, pro-

vides the reference source for the part. On the digital side, the

part is configured for three-wire operation with

CS tied to

GND. A quartz crystal or ceramic resonator provide the master

clock source for the part. In most cases, it will be necessary to

connect capacitors on the crystal or resonator to ensure that it

does not oscillate at overtones of its fundamental operating fre-

quency. The values of capacitors will vary, depending on the

manufacturer’s specifications. The same setup applies to the

AD7706.

VDD

ANALOG

+5V SUPPLY

10 F

AIN1(+)

AIN1(–)

AIN2(+)

AIN2(–)

DIFFERENTIAL

ANALOG

INPUT

DIFFERENTIAL

ANALOG

INPUT

GND

REF IN(+)

REF IN(–)

10 F

VIN

ANALOG +5V

SUPPLY

AD780/

REF192

VOUT

GND

AD7705

DRDY

DATA READY

DOUT

RECEIVE (READ)

DIN

SERIAL DATA

SCLK

SERIAL CLOCK

RESET

+5V

MCLK IN

MCLK OUT

CRYSTAL OR

CERAMIC

RESONATOR

0.1 F

Figure 10. AD7705 Basic Connection Diagram

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