2

–5–

REV. C

AD7713

Parameter

(A, S Versions)

Units

Conditions/Comments

External-Clocking Mode

MHz max

Serial Clock Input Frequency

0

ns min

DRDY

to RFS Setup Time

0

ns min

DRDY

to RFS Hold Time

2

× t

CLK IN

ns min

A0 to RFS Setup Time

0

ns min

A0 to RFS Hold Time

6

4

× t

CLK IN

ns max

Data Access Time (RFS Low to Data Valid)

6

10

ns min

SCLK Falling Edge to Data Valid Delay

2

× t

ns max

2

× t

CLK IN

ns min

SCLK High Pulse Width

2

× t

CLK IN

ns min

SCLK Low Pulse Width

ns max

SCLK Falling Edge to DRDY High

7

10

ns min

SCLK to Data Valid Hold Time

ns max

10

ns min

RFS

/TFS to SCLK Falling Edge Hold Time

7

5

× t

ns max

RFS

to Data Valid Hold Time

0

ns min

A0 to TFS Setup Time

0

ns min

A0 to TFS Hold Time

4

× t

CLK IN

ns min

SCLK Falling Edge to TFS Hold Time

2

× t

ns min

Data Valid to SCLK Setup Time

30

ns min

Data Valid to SCLK Hold Time

NOTES

device can draw higher current than specified and possibly become uncalibrated.

is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are

the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

TO OUTPUT

PIN

+2.1V

1.6mA

200µA

100pF

Figure 1. Load Circuit for Access Time and Bus Relinquish Time