AD7713 datasheet(24/28 Pages) AD

24 / 28 page

REV. C

–24–

AD7713

which is in its single chip mode. The DRDY line from the

AD7713 is connected to the Port PC0 input of the 68HC11 so

the DRDY line is polled by the 68HC11. The DRDY line can

be connected to the IRQ input of the 68HC11 if an interrupt

driven system is preferred. The 68HC11 MOSI and MISO lines

should be configured for wired-or operation. Depending on the

interface configuration, it may be necessary to provide bidirec-

tional buffers between the 68HC11’s MOSI and MISO lines.

The 68HC11 is configured in the master mode with its CPOL

bit set to a logic zero and its CPHA bit set to a logic one.

DVDD

SYNC

RFS

TFS

SDATA

SCLK

MODE

PC0

PC1

PC2

PC3

MISO

MOSI

68HC11

AD7713

DRDY

SCK

DVDD

Figure 18. AD7713 to 68HC11 Interface

AD7713 to ADSP-2105 Interface

An interface circuit between the AD7713 and the ADSP-2105

microprocessor is shown in Figure 19. In this interface, the

AD7713 is configured for its self-clocking mode while the RFS

and TFS pins of the ADSP-2105 are configured as inputs and

the ADSP-2105 serial clock line is also configured as an input.

When the ADSP-2105’s serial clock is configured as an input it

needs a couple of clock pulses to initialize itself correctly before

accepting data. Therefore, the first read from the AD7713 may

not read correct data. In the interface shown, a read operation

to the AD7713 accesses either the output register or the calibra-

tion registers. Data cannot be read from the control register. A

write operation always writes to the control or calibration

registers.

DRDY

is used as the frame synchronization pulse for read op-

erations from the output register and it is decoded with A0 to

drive the RFS inputs of both the AD7713 and the ADSP-2105.

The latched A0 line drives the TFS inputs of both the AD7713

and the ADSP-2105 as well as the AD7713 A0 input.

DVDD

SDATA

SCLK

MODE

ADSP-2105

AD7713

RFS

TFS

DRDY

RFS

TFS

74HC74

SCLK

DMWR

Figure 19. AD7713 to ADSP-2105 Interface

READ 1:

MOV A,SBUF;

Read Buffer

RLC A;

Rearrange Data

MOV B.0,C;

Reverse Order of Bits

RLC A; MOV B.1,C; RLC A; MOV B.2,C;

RLC A; MOV B.3,C; RLC A; MOV B.4,C;

RLC A; MOV B.5,C; RLC A; MOV B.6,C;

RLC A; MOV B.7,C;

MOV A,B;

MOV @R0,A; Write Data to Memory

INC R0;

Increment Memory Location

DEC R1

Decrement Byte Counter

MOV A,R1

JZ END

Jump if Zero

JMP WAIT

Fetch Next Byte

END:

SETB 90H

Bring RFS High

FIN:

SJMP FIN

Table VI. 8XC51 Code for Writing to the AD7713

MOV SCON,#00000000B;

Configure 8051 for MODE 0

Operation & Enable Serial Reception

MOV IE,#10010000B;

Enable Transmit Interrupt

MOV IP,#00010000B;

Prioritize the Transmit Interrupt

SETB 91H;

Bring TFS High

SETB 90H;

Bring RFS High

MOV R1,#003H;

Sets Number of Bytes to Be Written

in a Write Operation

MOV R0,#030H;

Start Address in RAM for Bytes

MOV A,#00H;

Clear Accumulator

MOV SBUF,A;

Initialize the Serial Port

WAIT:

JMP WAIT;

Wait for Interrupt

INT ROUTINE:

NOP;

Interrupt Subroutine

MOV A,R1;

Load R1 to Accumulator

JZ FIN;

If Zero Jump to FIN

DEC R1;

Decrement R1 Byte Counter

MOV A,@R;

Move Byte into the Accumulator

INC R0;

Increment Address

RLC A;

Rearrange Data—From LSB First

to MSB First

MOV B.0,C; RLC A; MOV B.1,C; RLC A;

MOV B.2,C; RLC A; MOV B.3,C; RLC A;

MOV B.4,C; RLC A; MOV B.5,C; RLC A;

MOV B.6,C; RLC A: MOV B.7,C; MOV A,B;

CLR 93H;

Bring A0 Low

CLR 91H;

Bring TFS Low

MOV SBUF,A;

Write to Serial Port

RETI;

Return from Subroutine

FIN:

SETB 91H;

Set TFS High

SETB 93H;

Set A0 High

RETI;

Return from Interrupt Subroutine

AD7713 to 68HC11 Interface

Figure 18 shows an interface between the AD7713 and the

68HC11 microcontroller. The AD7713 is configured for its ex-

ternal clocking mode while the SPI port is used on the 68HC11

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