AD7713 datasheet(20/28 Pages) AD

20 / 28 page

REV. C

–20–

AD7713

SDATA (I)

SCLK (O)

TFS (I)

A0 (I)

MSB

LSB

t14

t 9

t 15

t16

t 17

t18

t19

t10

Figure 11. Self-Clocking Mode, Control/Calibration Register Write Operation

Write Operation

Data can be written to either the control register or calibration

registers. In either case, the write operation is not affected by

the DRDY line and the write operation does not have any effect

on the status of DRDY. A write operation to the control register

or the calibration register must always write 24 bits to the

respective register.

Figure 11 shows a write operation to the AD7713. A0 deter-

mines whether a write operation transfers data to the control

main valid for the duration of the serial write operation. The

falling edge of TFS enables the internally generated SCLK out-

put. The serial data to be loaded to the AD7713 must be valid

on the rising edge of this SCLK signal. Data is clocked into the

AD7713 on the rising edge of the SCLK signal with the MSB

transferred first. On the last active high time of SCLK, the LSB

is loaded to the AD7713. Subsequent to the next falling edge of

SCLK, the SCLK output is turned off. (The timing diagram of

Figure 11 assumes a pull-up resistor on the SCLK line.)

External Clocking Mode

The AD7713 is configured for its external clocking mode by

tying the MODE pin low. In this mode, SCLK of the AD7713

is configured as an input, and an external serial clock must be

provided to this SCLK pin. This external clocking mode is

designed for direct interface to systems which provide a serial

clock output which is synchronized to the serial data output,

including microcontrollers such as the 80C51, 87C51, 68HC11

and 68HC05 and most digital signal processors.

Read Operation

As with the self-clocking mode, data can be read from either the

output register, the control register or the calibration registers.

A0 determines whether the data read accesses data from the

control register or from the output/calibration registers. This A0

signal must remain valid for the duration of the serial read op-

eration. With A0 high, data is accessed from either the output

accessed from the control register.

The function of the DRDY line is dependent only on the output

update rate of the device and the reading of the output data reg-

ister. DRDY goes low when a new data word is available in the

output data register. It is reset high when the last bit of data

(either 16th bit or 24th bit) is read from the output register. If

data is not read from the output register, the DRDY line will

remain low. The output register will continue to be updated at

the output update rate, but DRDY will not indicate this. A read

from the device in this circumstance will access the most recent

word in the output register. If a new data word becomes avail-

able to the output register while data is being read from the out-

put register, DRDY will not indicate this and the new data

word will be lost to the user. DRDY is not affected by reading

from the control register or the calibration register.

Data can only be accessed from the output data register when

DRDY

is low. If RFS goes low while DRDY is high, no data

transfer will take place. DRDY does not have any effect on

reading data from the control register or from the calibration regis-

ters.

Figures 12a and 12b show timing diagrams for reading from the

AD7713 in the external clocking mode. Figure 12a shows a

situation where all the data is read from the AD7713 in one

read operation. Figure 12b shows a situation where the data is

read from the AD7713 over a number of read operations. Both

read operations show a read from the AD7713’s output data

is similar, but in these cases the DRDY line is not related to the

read function. Depending on the output update rate, it can go

low at any stage in the control/calibration register read cycle

without affecting the read and its status should be ignored. A

read operation from either the control or calibration registers

must always read 24 bits of data from the respective register.

Figure 12a shows a read operation from the AD7713 where

RFS

remains low for the duration of the data word transmis-

sion. With DRDY low, the RFS input is brought low. The in-

put SCLK signal should be low between read and write

operations. RFS going low places the MSB of the word to be

read on the serial data line. All subsequent data bits are clocked

out on a high to low transition of the serial clock and are valid

prior to the following rising edge of this clock. The penultimate

falling edge of SCLK clocks out the LSB and the final falling

edge resets the DRDY line high. This rising edge of DRDY

turns off the serial data output.

Figure 12b shows a timing diagram for a read operation where

RFS

returns high during the transmission of the word and re-

turns low again to access the rest of the data word. Timing

parameters and functions are very similar to that outlined for

Figure 12a, but Figure 12b has a number of additional times to

show timing relationships when RFS returns high in the middle

of transferring a word.

RFS

should return high during a low time of SCLK. On the

rising edge of RFS, the SDATA output is turned off. DRDY

remains low and will remain low until all bits of the data word

are read from the AD7713, regardless of the number of times

RFS

changes state during the read operation. Depending on the

time between the falling edge of SCLK and the rising edge of

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