REV. A

AD8300

–7–

Table I. Control Logic Truth Table

CS

CLK

CLR

LD

Serial Shift Register Function

DAC Register Function

H

X

H

H

No Effect

Latched

L

L

H

H

No Effect

Latched

L

H

H

H

No Effect

Latched

L

↑

H

H

Shift-Register-Data Advanced One Bit

Latched

↑

L

H

H

No Effect

Latched

HX

H

↓

No Effect

Updated with Current Shift Register Contents

H

X

H

L

No Effect

Transparent

H

X

L

X

No Effect

Loaded with All Zeros

HX

↑

H

No Effect

Latched All Zeros

NOTES

1.

↑ = Positive Logic Transition; ↓ = Negative Logic Transition; X = Don’t Care.

2. Do not clock in serial data while

LD is LOW.

3. Data loads MSB first.

OPERATION

The AD8300 is a complete ready to use 12-bit digital-to-analog

converter. Only one +3 V power supply is necessary for opera-

tion. It contains a 12-bit laser-trimmed digital-to-analog

converter, a curvature-corrected bandgap reference, rail-to-rail

output op amp, serial-input register, and DAC register. The

serial data interface consists of a serial-data-input (SDI) clock

(CLK), and load strobe pins (

LD) with an active low CS strobe.

In addition an asynchronous

CLR pin will set all DAC register

tion is useful for power on reset or system failure recovery to a

known state.

D/A CONVERTER SECTION

The internal DAC is a 12-bit device with an output that swings

from GND potential to 0.4 volt generated from the internal band-

gap voltage, see Figure 20. It uses a laser-trimmed segmented

R-2R ladder which is switched by N-channel MOSFETs. The

output voltage of the DAC has a constant resistance indepen-

dent of digital input code. The DAC output is internally con-

nected to the rail-to-rail output op amp.

AMPLIFIER SECTION

The internal DAC’s output is buffered by a low power con-

sumption precision amplifier. This low power amplifier contains

a differential PNP pair input stage that provides low offset volt-

age and low noise, as well as the ability to amplify the zero-scale

DAC output voltages. The rail-to-rail amplifier is configured

with a gain of approximately five in order to set the 2.0475 volt

full-scale output (0.5 mV/LSB). See Figure 20 for an equivalent

circuit schematic of the analog section.

12-BIT DAC

R1

R2

2.047V

FS

1.2V

0.4V

0.4V

FS

BANDGAP

REF

Figure 20. Equivalent AD8300 Schematic of Analog Portion

The op amp has a 2

µs typical settling time to 0.4% of full scale.

There are slight differences in settling time for negative slewing

signals versus positive. Also negative transition settling time to

within the last 6 LSB of zero volts has an extended settling time.

See the oscilloscope photos in the typical performances section

of this data sheet.

OUTPUT SECTION

The rail-to-rail output stage of this amplifier has been designed

to provide precision performance while operating near either

power supply. Figure 21 shows an equivalent output schematic

of the rail-to-rail amplifier with its N-channel pull-down FETs

that will pull an output load directly to GND. The output

sourcing current is provided by a P-channel pull-up device that

can source current to GND terminated loads.

P-CH

N-CH

AGND

Figure 21. Equivalent Analog Output Circuit

The rail-to-rail output stage achieves the minimum operating

supply voltage capability shown in Figure 2. The N-channel

output pull-down MOSFET shown in Figure 21 has a 35

Ω on

resistance which sets the sink current capability near ground. In

addition to resistive load driving capability, the amplifier has

also been carefully designed and characterized for up to 500 pF

capacitive load driving capability.

REFERENCE SECTION

The internal curvature-corrected bandgap voltage reference is

laser trimmed for both initial accuracy and low temperature

coefficient. Figure 18 provides a histogram of total output per-

formance of full-scale vs. temperature which is dominated by

the reference performance.

POWER SUPPLY

The very low power consumption of the AD8300 is a direct

result of a circuit design optimizing use of a CBCMOS process.

By using the low power characteristics of the CMOS for the

logic, and the low noise, tight matching of the complementary

bipolar transistors, good analog accuracy is achieved.

For power-consumption sensitive applications it is important to

note that the internal power consumption of the AD8300 is

strongly dependent on the actual logic input voltage levels

present on the SDI, CLK,

CS, LD, and CLR pins. Since these

inputs are standard CMOS logic structures, they contribute

static power dissipation dependent on the actual driving logic