AD8300 datasheet(2/8 Pages) AD

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REV. A

–2–

AD8300–SPECIFICATIONS

+3 V OPERATION

Parameter

Symbol

Condition

Min

Typ

Max

Units

STATIC PERFORMANCE

Resolution

[Note 1]

Bits

Relative Accuracy

INL

–2

±1/2

LSB

Differential Nonlinearity

DNL

Monotonic

–1

±1/2

LSB

Zero-Scale Error

VZSE

Data = 000H

+1/2

Full-Scale Voltage3

VFS

Data = FFFH

2.039 2.0475 2.056

Volts

Full-Scale Tempco

TCVFS

[Notes 3, 4]

ppm/

°C

ANALOG OUTPUT

Output Current (Source)

IOUT

Data = 800H,

∆V

OUT = 5 LSB

Output Current (Sink)

IOUT

Data = 800H,

∆V

OUT = 5 LSB

Load Regulation

LREG

RL = 200 Ω to ∞, Data = 800H

1.5

LSB

Output Resistance to GND

ROUT

Data = 000H

Ω

Capacitive Load

No Oscillation

500

LOGIC INPUTS

Logic Input Low Voltage

VIL

0.6

Logic Input High Voltage

VIH

2.1

Input Leakage Current

IIL

µA

Input Capacitance

CIL

INTERFACE TIMING

SPECIFICATIONS

4, 5

Clock Width High

tCH

Clock Width Low

tCL

Load Pulsewidth

tLDW

Data Setup

tDS

Data Hold

tDH

Clear Pulsewidth

tCLRW

Load Setup

tLD1

Load Hold

tLD2

Select

tCSS

Deselect

tCSH

AC CHARACTERISTICS4

Voltage Output Settling Time

±0.2% of Full Scale

µs

±1 LSB of Final Value6

µs

Output Slew Rate

Data = 000H to FFFH to 000H

2.0

µs

DAC Glitch

nV/s

Digital Feedthrough

nV/s

SUPPLY CHARACTERISTICS

Power Supply Range

VDD RANGE

DNL <

±1 LSB

2.7

5.5

Positive Supply Current

IDD

VDD = 3 V, VIL = 0 V, Data = 000H

1.2

1.7

VDD = 3.6 V, VIH = 2.3 V, Data = FFFH

1.9

3.0

Power Dissipation

PDISS

VDD = 3 V, VIL = 0 V, Data = 000H

3.6

5.1

Power Supply Sensitivity

PSS

∆V

DD = ± 5%

0.001

0.005

%/%

NOTES

LSB = 0.5 mV for 0 V to +2.0475 V output range.

2The first two codes (000

H, 001H) are excluded from the linearity error measurement.

3Includes internal voltage reference error.

4These parameters are guaranteed by design and not subject to production testing.

5All input control signals are specified with t

R = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V.

6The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in

this 6 LSB region.

Specifications subject to change without notice.

(@ VDD = +5 V

10%, –40 C

≤ T

≤ +85 C, unless otherwise noted)

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