REV. A

AD8306

–13–

10 mV/dB The AD8031 rail-to-rail op amp, used in both ex-

amples, can swing from 50 mV to 4.95 mV on a single +5 V

supply. If high output current is required (> 10 mA), the AD8051,

which also has rail-to-rail capability but can deliver up to 45 mA

of output current, can be used.

APPLICATIONS

The AD8306 is a versatile and easily applied log-limiting ampli-

fier. Being complete, it can be used with very few external com-

ponents, and most applications can be accommodated using the

simple connections shown in the preceding section. A few ex-

amples of more specialized applications are provided here.

High Output Limiter Loading

The AD8306 can generate a fairly large output power at its

differential limiter output interface. This may be coupled into a

50

Ω grounded load using the narrow-band coupling network

following similar lines to those provided for input matching.

Alternatively, a flux-linked transformer, having a center-tapped

primary, may be used. Even higher output powers can be ob-

tained using emitter-followers. In Figure 31, the supply voltage

to the AD8306 is dropped from 5 V to about 4.2 V, by the

diode. This increases the available swing at each output to about

2 V. Taking both outputs differentially, a square wave output of

4 V p-p can be generated.

1

2

3

4

5

6

7

8

VLOG

VPS2

PADL

LMHI

LMLO

PADL

FLTR

LMDR

COM2

VPS1

PADL

INHI

INLO

PADL

COM1

ENBL

AD8306

9

10

11

14

15

16

0.1 F

10

RSSI

3V TO 5V

0.1 F

10

12

13

+5V

IN914

APPROX. 4.2V

5V TO 3V

DIFFERENTIAL

OUTPUT = 4V pk-pk

Figure 31. Increasing Limiter Output Voltage

When operating at high output power levels and high frequen-

cies, very careful attention must be paid to the issue of stability.

Oscillation is likely to be observed when the input signal level is

low, due to the extremely high gain-bandwidth product of the

AD8306 under such conditions. These oscillations will be less

evident when signal-balancing networks are used, operating at

frequencies below 200 MHz, and they will generally be fully

quenched by the signal at input levels of a few dB above the

noise floor.

Modulated Limiter Output

The limiter output stage of the AD8306 also provides an analog

multiplication capability: the amplitude of the output square

wave can be controlled by the current withdrawn from LMDR

(Pin 9). An analog control input of 0 V to +1 V is used to gener-

ate an exactly-proportional current of 0 mA to 10 mA in the npn

transistor, whose collector is held at a fixed voltage of

∼400 mV

by the internal bias in the AD8306. When the input signal is

above the limiting threshold, the output will then be a square-

wave whose amplitude is proportional to the control bias.

1

2

3

4

5

6

7

8

VLOG

VPS2

PADL

LMHI

LMLO

PADL

FLTR

LMDR

COM2

VPS1

PADL

INHI

INLO

PADL

COM1

ENBL

AD8306

9

10

11

14

15

16

10

10

12

13

1.8k

AD8031

0.1 F

RSSI

0.1 F

VARIABLE

OUTPUT

8.2k

0V TO +1V

18

0mA TO

10mA

2N3904

0.1 F

Figure 32. Variable Limiter Output Programming

Effect of Waveform Type on Intercept

The AD8306 fundamentally responds to voltage and not to

power. A direct consequence of this characteristic is that input

signals of equal rms power, but differing crest factors, will pro-

duce different results at the log amp’s output.

The effect of differing signal waveforms is to shift the effective

value of the log amp’s intercept. Graphically, this looks like a

vertical shift in the log amp’s transfer function. The device’s

logarithmic slope however is not affected. For example, consider

the case of the AD8306 being alternately fed by an unmodu-

lated sine wave and by a single CDMA channel of the same rms

power. The AD8306’s output voltage will differ by the equiva-

lent of 3.55 dB (71 mV) over the complete dynamic range of the

device (the output for a CDMA input being lower).

Table II shows the correction factors that should be applied to

measure the rms signal strength of a various signal types. A sine

wave input is used as a reference. To measure the rms power of

a square wave, for example, the mV equivalent of the dB value

given in the table (20 mV/dB times 3.01 dB) should be sub-

tracted from the output voltage of the AD8306.

Table II. Shift in AD8306 Output for Signals with Differing

Crest Factors

Correction Factor

Signal Type

(Add to Output Reading)

Sine Wave

0 dB

Square Wave or DC

–3.01 dB

Triangular Wave

+0.9 dB

GSM Channel (All Time Slots On)

+0.55 dB

CDMA Channel (Forward Link, 9

Channels On)

+3.55 dB

CDMA Channel (Reverse Link)

+0.5 dB

PDC Channel (All Time Slots On) +0.58 dB

Gaussian Noise

+2.51 dB

Evaluation Board

An evaluation board, carefully laid out and tested to demon-

strate the specified high speed performance of the AD8306 is

available. Figure 33 shows the schematic of the evaluation

board, which fairly closely follows the basic connections sche-

matic shown in Figure 27. For ordering information, please

refer to the Ordering Guide. Links, switches and component

settings for different setups are described in Table III.