REV. 0

AD8326

–6–

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Description

1

DATEN

Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic

0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta-

neously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch

(holds the previous gain state) and simultaneously enables the register for serial data load.

2

SDATA

Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the

internal register with the MSB (Most Significant Bit) first and ignored.

3

CLK

Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-

slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to

the slave. This requires the input serial data word to be valid at or before this clock transition.

4, 28

GND

Common External Ground Reference

5, 9, 10, 19,

Common Positive External Supply Voltage. A 0.1

µF capacitor must decouple each pin.

20, 23, 27

6

TXEN

Transmit Enable pin. Logic 1 powers up the part.

7

SLEEP

Low Power Sleep Mode. In the Sleep mode, the AD8326’s supply current is reduced to 4 mA. A

8, 12, 17

NC

No Connection to these pins.

11, 13, 16, 18,

Common Negative External Supply Voltage. A 0.1

µF capacitor must decouple each pin.

22, 24

14

OUT–

Negative Output Signal

15

OUT+

Positive Output Signal

21

BYP

Internal Bypass. This pin must be externally ac-coupled (0.1

µF capacitor).

25

0.1

µF capacitor.

26

µF capacitor.

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

AD8326

DATEN

GND

SDATA

CLK

GND

TXEN

SLEEP

NC

BYP

NC

NC

OUT–

OUT+

NC = NO CONNECT