REV. 0

AD8345

–4–

PIN FUNCTION DESCRIPTIONS

Equivalent

Pin No.

Mnemonic

Function

Circuit

1, 2

IBBP, IBBN

I Channel Baseband Differential Input Pins. These high impedance inputs should

Circuit A

be dc biased to approximately 0.7 V. Nominal characterized ac swing is 0.6 V p-p

on each pin (0.4 V to 1 V). This gives a differential drive of 1.2 V p-p. Inputs are

not self-biasing so external biasing circuitry must be used in ac-coupled applications.

3, 9, 13, 14

COM3

Ground Pin for Input V-to-I Converters and Mixer Core.

4

COM1

Ground Pin for the LO Phase-Splitter and LO Buffers.

5, 6

LOIN, LOIP

Circuit B

is supplied. Pins must be ac-coupled. Single-ended or differential drive is permissible.

7

VPS1

Power Supply Pin for the Bias Cell and LO Buffers. This pin should be decoupled

using local 1000 pF and 0.01

µF capacitors.

8

ENBL

Enable Pin. A high level enables the device; a low level puts the device in sleep mode. Circuit C

10

COM2

Ground Pin for the Output Stage of Output Amplifier.

11

VOUT

50

Ω DC-Coupled RF Output. Pin should be ac-coupled.

Circuit D

12

VPS2

Power supply pin for baseband input voltage to current converters and mixer core.

This pin should be decoupled using local 1000 pF and 0.01

µF capacitors.

15, 16

QBBN, QBBP

Q Channel Baseband Differential Input Pins. Inputs should be dc biased to

Circuit A

approximately 0.7 V. Nominal characterized ac swing is 0.6 V p-p on each pin

(0.4 V to 1 V). This gives a differential drive level of 1.2 V p-p. Inputs are not

self-biasing so external biasing circuitry must be used in ac-coupled applications.

EQUIVALENT CIRCUITS

INPUT

CURRENT

MIRROR

TO MIXER

CORE

BUFFER

VPS2

Circuit A

PHASE

SPLITTER

CONTINUES

LOIN

VPS1

LOIP

Circuit B

ENBL

100k

VPS2

100k

100k

TO BIAS FOR

STARTUP/

SHUTDOWN

Circuit C

40

40

VPS2

VOUT

Circuit D

Figure 1. Equivalent Circuits