ADMC300BST datasheet(10/42 Pages) AD

10 / 42 page

ADMC300

–10–

REV. B

PIN FUNCTION DESCRIPTION

The ADMC300 is available in an 80-lead TQFP package. Table I

contains the pin descriptions.

Table I. Pin List

Group

Input/

Name

Pins Output

Function

RESET

Processor Reset Input.

SPORT0

I/O

Serial Port 0 Pins (TFS0, RFS0,

DT0, DR0, SCLK0).

SPORT1

I/O

Serial Port 1 Pins (TFS1,

RFS1, DT1, DR1A, DR1B,

SCLK1).

CLKOUT

Processor Clock Output.

CLKIN, XTAL

I, O

External Clock or Quartz Crystal

Connection Point.

PIO0–PIO11

I/O

Digital I/O Port, External Con-

vert Start and Event Timer

Pins.

AUX0–AUX1

Auxiliary PWM Outputs.

AH–CL

PWM Outputs.

PWMTRIP

PWM Trip Signal.

PWMPOL

PWM Polarity Pin.

PWMSYNC

PWM Synchronization Pin.

V1–V5

Noninverting Inputs of the Dif-

ferential ADCs’ Input Amplifiers.

V1N–V5N

Inverting Inputs of the Differen-

tial ADCs’ Input Amplifiers.

REFINA–

Voltage reference inputs for

REFINB

ADCs.

VREF

Voltage Reference Output.

MUX0–MUX2

Multiplexer Control Lines.

EIA, EIB, EIZP

Encoder Interface Pins.

AVDD

Analog Power Supply.

AGND

Analog Ground.

VDD

Digital Power Supply.

GND

Digital Ground.

INTERRUPT OVERVIEW

The ADMC300 can respond to nineteen different interrupt

sources, eight of which are internal DSP core interrupts and

eleven interrupts from the motor control peripherals. The eight

DSP core interrupts comprise the peripheral (

IRQ2), SPORT0

receive, SPORT0 transmit, SPORT1 receive (or

IRQ0), SPORT1

transmit (or

IRQ1), two software and the interval timer interrupts.

In addition, the motor control peripherals add eleven interrupts

that include two ADC, two PWM, five peripheral I/O, one en-

coder interface and one event timer interrupt. The interrupts are

internally prioritized and individually maskable. All peripheral

interrupts are multiplexed into the DSP core through the pe-

ripheral

IRQ2 interrupt. The programmable interrupt controller

manages the masking and vector addressing of all eleven periph-

eral interrupts. A detailed description of the operation of the

entire interrupt system of the ADMC300 is given later, after a

more detailed description of the various peripheral systems.

Memory Map

The ADMC300 has two distinct memory types; program

memory and data memory. In general, program memory con-

tains user code and coefficients, while the data memory is used

to store variables and data during program execution. Both pro-

gram memory RAM and ROM is provided on the ADMC300.

Program memory RAM is arranged in two noncontiguous 2K

24-bit blocks, one starting at address 0x0000 and the other at

0x1800. Program memory ROM is located at address 0x0800.

Data memory is arranged as a 1K

× 16-bit block starting at

address 0x3800. The motor control peripherals are memory

mapped into a region of the data memory space starting at

0x2000. The complete program and data memory maps are

given in Tables II and III respectively.

Table II. Program Memory Map

Memory

Address Range

Type

Function

0x0000–0x005F

RAM

Interrupt Vector Table

0x0060–0x071F

RAM

User Program Space

0x0720–0x07DF

RAM

Reserved by Debugger

0x07E0–0x07FF

RAM

Reserved by Monitor

0x0800–0x0E20

ROM

ROM Monitor

0xE21–0xFD6

ROM

ROM Math and Motor

Control Utilities

0xFD7–0x0FFF

ROM

Reserved

0x1000–0x17FF

Unused

0x1800–0x1FFF

RAM

User Program Space

0x2000–0x3FFF

Unused

Table III. Data Memory Map

Memory

Address Range

Type

Function

0x0000–0x1FFF

Unused

0x2000–0x20FF

Memory Mapped Registers

0x2100–0x37FF

Unused

0x3800–0x3B5F

RAM

User Data Space

0x3B60–0x3BFF

RAM

Reserved by Monitor

0x3C00–0x3FFF

Memory Mapped Registers

ROM Code

The 2K

× 24-bit block of program memory ROM starting at ad-

dress 0x0800 contains a monitor function that is used to download

and execute user programs via the serial port. In addition, the

monitor function supports an interactive mode in which com-

mands are received and processed from a host. An example of such

a host is the Windows

®-based Motion Control Debugger that is

part of the software development system for the ADMC300. In

the interactive mode, the host can access both the internal DSP

and peripheral motor control registers of the ADMC300, read and

write to both program and data memory, implement breakpoints

and perform single-step and run/halt operation as part of the pro-

gram debugging cycle.

In addition to the monitor function, the program memory ROM

contains a number of useful mathematical and motor control util-

ities that can be called as subroutines from the user code. A com-

plete list of these ROM functions is given in Table IV. The start

address of the function in the program memory ROM is also given.

Refer to the ADMC300 DSP Motor Controller Developer’s Reference

Manual for more details of the ROM functions.

Windows is a registered trademark of Microsoft Corporation.

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