ADMC300

–33–

REV. B

0

0

0

0

0

0

0

0

0

0

00

0

0

0

DM (0x2037)

BUSY SIGNAL

ADCSTAT (R)

0 = NORMAL

1 = FILTERS BUSY

SETTLING

0

0

0

0

0

0

0

0

0

0

1

1

1

1

0

0

ADCCTRL (R/W)

DM (0x2036)

BANK A CONVERT START

0 = INTERNAL

1 = EXTERNAL

BANK B CONVERT START

BANK A MODE

0 = CONVST

1 = READ

BANK B MODE

MUX0 CONTROL

0 = LOW

1 = HIGH

MUX1 CONTROL

MUX2 CONTROL

BANK A

SYNCHRONIZATION

0 = DISABLE

1 = ENABLE

BANK B

SYNCHRONIZATION

0 = NORMAL

1 = RESET

FILTER MODE

0 = NORMAL

1 = RESET

MODULATOR MODE

RESERVED (SET TO 1)

REFERENCE

POWER-DOWN

0 = POWER-ON

1 = POWER-DOWN

BANK B

POWER-DOWN

0 = POWER-ON

1 = POWER-DOWN

BANK A

POWER-DOWN

BUSY SIGNAL

0 = BANK A

1 = BANK B

ADC1 (R)

ADC2 (R)

ADC3 (R)

ADC4 (R)

ADC5 (R)

DM (0x2030)

DM (0x2031)

DM (0x2032)

DM (0x2033)

DM (0x2034)

DM (0x2038)

RELATIVE PHASE

OF PWMSYNC TO

ADC CONVST

ADCSYNC (R/W)

0

0

00

0

0

0

0

0

0

0

00

0

0

0

15

14

13

12

11

10

9

876

5432

10

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

13

12

11

10

9

876

5432

10

Figure 20. Configuration of ADMC300 Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset for R/W registers. Reserved bits are shown on a

gray field – these bits should always be written as shown.