ADMC300BST datasheet(32/42 Pages) AD

32 / 42 page

ADMC300

–32–

REV. B

Table VIII. Peripheral Register Map of ADMC300 (Continued)

Address

Name

Bits

Function

0x2051

ETUB0

[15 . . . 0]

Event Timer Event B—Channel 0

0x2052

ETUAA0

[15 . . . 0]

Event Timer Event AA—Channel 0

0x2053

ETUA1

[15 . . . 0]

Event Timer A—Channnel 1

0x2054

ETUB1

[15 . . . 0]

Event Timer Event B—Channel 1

0x2055

ETUAA1

[15 . . . 0]

Event Timer Event AA—Channel 1

0x2056

ETUTIME

[15 . . . 0]

ETU Timer Register

0x2057–0x205B

Reserved

0x205C

ETUCONFIG

[7 . . . 0]

Event Timer Configuration

0x205D

ETUDIVIDE

[15 . . . 0]

Event Timer Clock Divide Register

0x205E

ETUSTAT

[1 . . . 0]

Event Timer Status Register

0x205F

ETUCTRL

[1 . . . 0]

Event Timer Control Register

0x2060

PWMSYNCWT

[7 . . . 0]

PWMSYNC Pulsewidth Control Register

0x2061

PWMSWT

[0]

PWM Software Trip Register

0x2062-0x20FF

Reserved

Table IX. DSP Core Registers

Address

Name

Bits

Function

0x3FFF

SYSCNTL

[15 . . . 0]

System Control Register

0x3FFE

MEMWAIT

[15 . . . 0]

Memory Wait State Control Register

0x3FFD

TPERIOD

[15 . . . 0]

Interval Timer Period Register

0x3FFC

TCOUNT

[15 . . . 0]

Interval Timer Count Register

0x3FFB

TSCALE

[7 ...0]

Interval Timer Scale Register

0x3FFA

SPORT0_RX_WORDS1

[15 . . . 0]

SPORT0 Multichannel Word 1 Receive

0x3FF9

SPORT0_RX_WORDS0

[15 . . . 0]

SPORT0 Multichannel Word 0 Receive

0x3FF8

SPORT0_TX_WORDS1

[15 . . . 0]

SPORT0 Multichannel Word 1 Transmit

0x3FF7

SPORT0_TX_WORDS0

[15 . . . 0]

SPORT0 Multichannel Word 0 Transmit

0x3FF6

SPORT0_CTRL_REG

[15 . . . 0]

SPORT0 Control Register

0x3FF5

SPORT0_SCLKDIV

[15 . . . 0]

SPORT0 Clock Divide Register

0x3FF4

SPORT0_RFSDIV

[15 . . . 0]

SPORT0 Receive Frame Sync Divide

0x3FF3

SPORT0_AUTOBUF_CTRL

[15 . . . 0]

SPORT0 Autobuffer Control Register

0x3FF2

SPORT1_CTRL_REG

[15 . . . 0]

SPORT1 Control Register

0x3FF1

SPORT1_SCLKDIV

[15 . . . 0]

SPORT1 Clock Divide Register

0x3FF0

SPORT1_RFSDIV

[15 . . . 0]

SPORT1 Receive Frame Sync Divide

0x3FEF

SPORT1_AUTOBUF_CTRL

[15 . . . 0]

SPORT1 Autobuffer Control Register

ADMC300BST Datasheet(PDF) 32 Page - Analog Devices

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