ADMC300BST datasheet(16/42 Pages) AD

16 / 42 page

ADMC300

–16–

REV. B

ADC Group Delay

The digital filters of the ADCs carry out two important func-

tions. First, they remove the out-of-band quantization noise,

which has been suitably shaped by the noise-shaping circuits of

the input modulator stages. The digital filters then decimate the

high frequency bitstream from the modulators to a lower rate

16-bit word. The lower rate is set by the ADC divide registers

for the respective ADC banks as described previously. The

antialiasing decimation filter may be modeled by the Z-domain

transfer function:

HSINC(Z )

− z−64

− z−1





















Associated with the sinc filters is a group delay that may be

approximated by:

tφ =

1.5

where fS is the update rate of the particular ADC channel. In

order to minimize the impact of the group delay on the overall

performance of the control system, it is advantageous to over-

sample the ADCs at a rate faster than the PWM frequency.

ADC Calibration

The ADC system of the ADMC300 has a calibration feature

that may be used to null any offsets in the ADC channels. There

is a 5-bit ADC calibration register, ADCCAL that has a dedi-

cated bit for each ADC channel. Setting the appropriate bit of

the ADCCAL register will place the respective ADC channel in

the offset calibration state. Bit 0 controls ADC1, Bit 1 con-

trols ADC2, etc. When the appropriate bit of the ADCCAL

nel are effectively disconnected from the pins of the ADMC300

and connected internally to the reference voltage. After wait-

ing for the settling time of the decimation filters, the resultant

ADC code is a measure of the offset for that particular ADC

channel. This number should be saved in memory and used to

correct all further measurements from that channel.

ADC Interrupt Generation

Two dedicated interrupts are associated with the ADC system

of the ADMC300, one for each of the ADC banks. The inter-

rupts are generated after the ADC data registers of the particu-

lar bank have been updated by either an internal or external

CONVST pulse. Interrupts are not generated when the ADCs

are in the read mode. There are separate interrupt vector loca-

tions associated with each of the interrupt sources. The ADC

Bank A interrupt is the highest priority interrupt with its vector

address at program memory location 0x0030. The Bank B

interrupt is the third highest priority interrupt with a vector

address of 0x0038. Each interrupt has a four word space in the

vector table. The sequencing and masking of these interrupts is

managed by the Programmable Interrupt Controller (PIC)

block described later.

ADC Multiplexer Control

The ADMC300 has three digital output pins, MUX2, MUX1

and MUX0, that can be used to drive an external multiplexer to

feed additional analog inputs to the ADCs if required. Using

these control lines, up to eight analog signals could be exter-

nally multiplexed into each ADC channel, allowing expansion

up to 40 analog inputs. The state of the three multiplexer pins

is directly controlled from the ADCCTRL register, using Bits

4–6. Bit 4 of the ADCCTRL register directly controls the

MUX0 pin, so that setting this bit will place a HI level on the

MUX0 pin. Similarly, Bit 5 directly controls the MUX1 pin

and Bit 6 controls the MUX2 pin.

Because of the finite impulse response of the decimation filters

of the ADCs, it is usually only slower dynamic signals that are

multiplexed into the ADCs. In a typical motor control system,

such signals may comprise the dc link voltage, the output of

various temperature sensors, reference inputs, etc.

ADC Status

Because of the dynamic characteristics of the decimation filters

of the sigma-delta converters, it is necessary to allow the

impulse response of the filters to decay before meaningful,

accurate data is available. There is a one-bit status register,

ADCSTAT, in the ADMC300 that indicates whether or not

valid data is available from the ADC. Bit 0 of the ADCSTAT

indicate that data is not yet valid. This BUSY bit can be pro-

grammed to represent the status of the decimation filters of either

Bank A or Bank B by programming Bit 9 of the ADCCTRL

periods any time that ADCCTRL, ADCCAL or ADCSYNC

are written to. If Bit 9 of the ADCCTRL register is cleared, the

BUSY bit will go active any time ADCDIVA is written to, and the

four ADC sample period width of the BUSY pulse will be four

ADC Bank A sample periods. If Bit 9 of the ADCCTRL register

is set, the BUSY bit will go active any time the ADCDIVB

the BUSY pulse will be four ADC Bank B sample periods. It is

still possible to read the ADC data registers while the BUSY

signal is asserted. However, care must be taken in the interpre-

tation of such data.

ADC Power-Down and Reset Features

The ADC section of the ADMC300 has certain power-down

features that may be used to reduce the overall power consump-

tion of the part. Each bank of the ADC system may be individually

powered down if all channels of that bank are not used in a par-

ticular application. Setting Bit 10 of the ADCCTRL register will

power down the input modulators of both ADC channels of

ADC Bank A. Similarly, setting Bit 11 of the ADCCTRL

Clearing these bits will enable the input modulators of the

respective banks. On power-up, both Bits 10 and 11 of the

ADCCTRL register are set by default, so that all five input

modulator stages are disabled. To operate the required ADC

channels, the appropriate bits in the ADCCTRL register must

be cleared.

In addition, setting Bit 12 of the ADCCTRL register will

power down the internal reference circuitry. Further power

reduction is possible if this reference circuitry is powered down.

However, this bit has an effect only if both ADC banks are also

powered down. Clearing Bit 12 of the ADCCTRL register will

enable the internal reference circuitry.

It is also possible to force a reset of all five input modulators of

the ADC system by setting Bit 14 of the ADCCTRL register.

Setting Bit 15 of the ADCCTRL register will force a reset of

the decimation filters in all five ADC channels. In order to

come out of input modulator reset or decimation filter reset,

the respective bit must be cleared. On power-up, these bits are

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