ADMC300BST datasheet(26/42 Pages) AD

26 / 42 page

ADMC300

–26–

REV. B

EIU/EET Registers

The EIU and EET registers are summarized at the end of the

data sheet.

PROGRAMMABLE INPUT/OUTPUT

The ADMC300 has 12 programmable digital input/output pins

called PIO0 to PIO11. Each pin may be individually configured

as either an input or an output. An associated data register may

be used to read data from pins configured as inputs and write

data to pins configured as outputs. In addition, each I/O line

may be configured as an interrupt source. Both edge (rising and

falling) and level (high and low) interrupts may be detected.

Four of the PIO lines (PIO0 to PIO3) have dedicated vector

addresses in the interrupt table. The remaining eight interrupts

(PIO4 to PIO11) are multiplexed into a single additional inter-

rupt vector location. The PIOFLAG register is used to deter-

mine which line caused the interrupt.

In addition, all PIO lines may be alternatively configured as

PWM trip sources. The PIOPWM register has dedicated bits

that may be used to enable this function on each PIO line. In

this mode, a low level on any pin configured as a PWM trip source

shuts down the PWM in a manner identical to the

PWMTRIP pin.

PIO Configuration

Each of the 12 programmable input/output lines may be config-

ured as either an input or an output by programming the appro-

priate bits of the PIODIR register. This 12-bit read/write register

has one bit associated with each I/O line; Bit 0 corresponds to

PIO0, etc. Clearing a bit in the PIODIR register will configure

the corresponding pin as an input pin. Conversely, setting a bit

configures the pin as an output pin. On reset, bits of the PIODIR

inputs. In addition, all PIO lines are internally pulled down in

the ADMC300 so that unconnected lines are seen as low level

inputs.

Three of the PIO lines also serve alternate functions. PIO9 is

multiplexed as the external convert start signal for the ADC

system. Signals on this pin can be used to trigger updating of

the ADC data registers, if required. Also, PIO10 and PIO11

may be used as inputs to the Event Timer Unit (ETU) to accu-

rately time the period, frequency or duty cycle of external sig-

nals. If these functions are not required, the three pins may be

used as general purpose I/O lines.

PIO Data Reading/Writing

Associated with the PIO system is a data register, PIODATA,

that also has a bit associated with each I/O line. Data written to

the PIODATA register will appear on those pins configured as

outputs. In addition, reading the PIODATA register will read

the data from those pins configured as inputs.

PIO Interrupt Generation

Each of the twelve PIO lines may be configured as an interrupt

source. Four of the PIO lines, PIO0 to PIO3, have dedicated

interrupt vector locations while the remaining eight are multi-

plexed into an additional interrupt vector. The PIOINTEN

enable function is used to enable or disable interrupts on the

PIO4 to PIO11 lines. The PICMASK register of the program-

mable interrupt controller is used to enable interrupts on the

four dedicated PIO lines, PIO0 to PIO3. Interrupts may be

generated on either edge (rising or falling) or level (high or

low) events by programming the appropriate bits of both the

PIOMODE and PIOLEVEL registers. Both registers have a

dedicated bit for each of the twelve PIO lines. Setting the appro-

priate bit of the PIOMODE register configures the interrupt as

level-sensitive, while clearing the bit configures the correspond-

ing PIO to be edge sensitive. In level-sensitive mode

(PIOMODE bit is 1), setting the corresponding bit in the

PIOLEVEL register configures the interrupt as active high,

while clearing the bit in the PIOLEVEL register configures it for

active low. In edge-sensitive mode (PIOMODE bit is 0), setting

the corresponding bit of the PIOLEVEL register configures the

interrupt for rising edge, while clearing the bit configures the

interrupt for falling edge. On reset, all PIO interrupts are dis-

abled. The appropriate register settings for correct PIO inter-

rupt configuration is shown in Table VI.

Table VI. PIO Interrupt Configuration

PIOMODE

PIOLEVEL

Falling Edge

Active Low

Rising Edge

Active High

The four dedicated PIO interrupts from PIO0 to PIO3 have

interrupt vector addresses at program memory addresses 0x0048

for PIO0, 0x004C for PIO1, 0x0050 for PIO2 and 0x0054 for

PIO3. In the event of an interrupt on PIO4 to PIO11, the cor-

responding bit of the PIOFLAG register is set and the general

PIO interrupt is activated. This interrupt has a dedicated vector

address at location 0x003C. In the interrupt service routine for

this interrupt, the user must poll the PIOFLAG register to de-

termine which of the PIO4 to PIO11 lines, that have interrupts

enabled, caused the interrupt. Of course, if only one of the PIO4 to

PIO11 lines have interrupts enabled, no polling is necessary.

Reading the PIOFLAG register clears all bits of the register.

PIO lines that are configured as outputs may also be used to

generate interrupts. If, for example, one of the PIO lines is

configured simultaneously as an output and as an interrupt

source, writing the appropriate data to the PIODATA register

will trigger an interrupt.

PIO as PWM Trip Sources

By setting the appropriate bits of the PIOPWM register, each of

the twelve PIO lines can be configured as a PWM trip source.

In this mode, a low level on the PIO pin will cause a PWM trip

that will disable all six PWM outputs on AH to CL. The dis-

abling of the PWM is independent of the DSP clock, so that the

PWM stage can be fully protected even in the event of a loss of

clock signal to the DSP.

PWMTRIP interrupt will be generated when the PWM is

reset (whether the PWM is reset via a PIO configured as a trip

source, or via the

PWMTRIP pin). It is also possible to generate

the normal PIO interrupts on the occurrence of a falling-edge

on the PIO line. The advantage of this highly flexible structure

for PWM shutdown is that multiple fault signals could be ap-

plied to the ADMC300 at different PIO lines. The occurrence

of a falling-edge on any of them will instantaneously shut down

the PWM. However, based on the particular PIO interrupt that

is flagged, the user can easily determine the source of the trip.

This permits the action of the interrupt service routines follow-

ing a PWM trip to be tailored to the particular fault that occurred.

On reset, all PIO lines are configured as PWM trip sources.

Because all PIO lines are also configured as inputs and have

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