ADV7160 datasheet(39/44 Pages) AD

39 / 44 page

ADV7160/ADV7162

REV. 0

–39–

Example

Color Mode: 24-Bit Gamma Corrected True Color (30-Bits) through Color Palette

Multiplexing: 2:1, Databus: 10-Bit, RAM-DAC Resolution: 10-Bit,

SYNC: on Green, Pedestal: 0 IRE, Calibration: Every Vertical Sync, Internal PLL: 220 MHz (Reference = 15 MHz)

C1 C0

R/W

Comment

Write 07H to Mode Register (MR1)

Resets ADV7162*

Write 06H to Mode Register (MR1)

10-Bit Data Bus, 10-Bit DAC Resolution

Write 07H to Mode Register (MR1)

Write 05H to Address Register (A7–A0)

Address Reg points to Command Register 1 (CR1)

Write 09H to Command Register 1 (CR1)

High byte access, Calibrate every Vertical Sync

Write 06H to Address Register (A7–A0)

Write 00H to Address Register (A10–A8)

Address Reg points to Command Register 2 (CR2)

Write E4H to Command Reg 2 (CR2)

24-Bit True Color, 0 IRE, Sync on Green

Write 07H to Address Register (A7–A0)

Write 00H to Address Register (A10–A8)

Address Reg points to Command Register 3 (CR3)

Write 40H to Command Reg 3 (CR3)

2:1 Muxing, PRGCKOUT = CLOCK

÷ 4

Write 08H to Address Register (A7–A0)

Write 00H to Address Register (A10–A8)

Address Reg points to Command Register 4 (CR4)

Write 00H to Command Reg 4 (CR4)

DAC GAIN = 3996

Write 0DH to Address Register (A7–A0)

Write 00H to Address Register (A10–A8)

Address Reg points to Command Register 5 (CR5)

Write 40H to Command Reg 5 (CR5)

Internal PLL to be used

Write 04H to Address Register (A7–A0)

Write 00H to Address Register (A10–A8)

Address Reg points to Pixel Mask Register

Write FFH to Pixel Mask Register

Set up Pixel Mask

Write 0FH to Address Register (A7–A0)

Write 00H to Address Register (A10–A8)

Address Reg points to PLL V Register

Write 09H to PLL V Register

Set up V value

Write 0CH to Address Register (A7–A0)

Write 00H to Address Register (A10–A8)

Address Reg points to PLL R Register

Write 01H to PLL R Register

Set up R value

Write 09H to Address Register (A7–A0)

Write 00H to Address Register (A10–A8)

Address Reg points to PLL Command Register (PCR)

Write 06H to PLL Command Register

Set up PCR as required

Color Palette RAM Initialization

C1 C0

R/W

Comment

Write 00H to Address Register (A7–A0)

Write 00H to Address Register (A10–A8)

Points to Color Palette RAM

Write 00H (red data) to RAM location (00H)

(Initializes Palette RAM

Write 00H (green data) to RAM location (00H)

(to a Linear Ramp**

Write 00H (blue data) to RAM location (00H)

(

Write 01H (red data) to RAM location (01H)

(

Write 01H (green data) to RAM location (01H)

(

Write 01H (blue data) to RAM location (01H)

(

Write FFH (red data) to RAM location (FFH)

(

Write FFH (green data) to RAM location (FFH)

(

Write FFH (blue data) to RAM location (FFH)

( RAM Initialization Complete

**These command lines reset the ADV7162. The pipelines for each of the Red, Green & Blue pixel inputs are synchronously reset to the Multiplexer's “A” input.

Mode Register bit MR10 is written by a “1” followed by “0” followed by “1.”

**This sequence of instructions would, of course, normally be coded using some form of loop instruction.

ADV7160 Datasheet(PDF) 39 Page - Analog Devices

ADV7160 Datasheet(HTML) 39 Page - Analog Devices

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