ADV7160 datasheet(29/44 Pages) AD

29 / 44 page

ADV7160/ADV7162

REV. 0

–29–

Figure 42. Command Register 3 (CR3) (CR39–CR30)

COMMAND REGISTER 4 (CR4)

(ADDRESS REG (A10–A0) = 008H)

This register contains a number of control bits as shown in the

diagram. CR4 is a 10-bit wide register. However for program-

ming purposes, it may be considered as an 8-bit wide register

(CR49 and CR48 are both reserved).

Figure 43 shows the various operations under the control of

CR4. This register can be read from as well written to. In read

mode, CR49 and CR48 are both returned as zeros.

COMMAND REGISTER 4-BIT DESCRIPTION

HDTV SYNC Enable (CR40)

This bit specifies whether the video TRISYNC Input is to be

encoded, enabling the DAC outputs to generate a Tri-Level

Sync.

SYNC

Recognition Control on Red (CR41)

This bit specifies whether the video SYNC Input is to be en-

coded onto the IOR analog output or ignored.

SYNC

Recognition Control on Blue (CR42)

This bit specifies whether the video SYNC Input is to be en-

coded onto the IOB analog output or ignored.

Gain Control (CR44–CR43)

These bits specifies the amount of gain on the DAC depending

on the standard required. See “DAC and Video Outputs” sec-

tion for more detail. For gain settings that have no pedestal, the

pedestal is automatically disabled independently of CR23.

Signature Clock Control (CR45)

This bit enables or disables the clock to the signature analyzer.

Figure 43. Command Register 4 (CR4) (CRF49–CR40)

HDTV SYNC CONTROL

SYNC RECOGNITION

CONTROL (RED)

SYNC RECOGNITION

CONTROL (BLUE)

DAC GAIN

CR44 CR43

Reserved*

CR49

CR48

CR47

CR46

CR45

CR42

CR41

CR40

SIGNATURE CLOCK

CONTROL

CR46

SIGNATURE RESET

SIGNATURE ACQUIRE

CR47

*THESE BITS ARE READ-ONLY

RESERVED BITS.

A READ CYCLE WILL RETURN

ZEROS "00."

CR45

CR42

CR41

CR40

IGNORE

DECODE

IGNORE

DECODE

DISABLE TRI-SYNC

ENABLE TRI-SYNC

ENABLE

DISABLE

ENABLE

DISABLE CLOCK

ENABLE CLOCK

3996

4224

4311

5592

CR44

CR43

RESERVED*

CR31 CR30

CLOCK

÷ 4

CLOCK

÷ 8

CLOCK

÷ 16

CLOCK

÷ 32

PRGCKOUT FREQUENCY

CONTROL

CR39

CR38

CR35

*THESE BITS ARE READ-ONLY

RESERVED BITS.

A READ CYCLE WILL RETURN

ZEROS "00."

CR37

CR36

CR34

CR33

CR32

CR37

CR36

EXTRA BLANK PIPELINE DELAY CONTROL

(ADDS TO PIXEL PIPELINE DELAY; tPD)

tPD

tPD + 1 x LOADOUT

tPD + 2 x LOADOUT

.........

tPD + 7 x LOADOUT

CR34 CR33 CR32

BLANK PIPELINE DELAY

CR35

(0)

CR37 CR36

1:1 MUXING: LOADOUT = CLOCK

÷ 1

2:1 MUXING: LOADOUT = CLOCK

÷ 2

8:1 MUXING: LOADOUT = CLOCK

÷ 8 (PSEUDO COLOR ONLY)

4:1 MUXING: LOADOUT = CLOCK

÷ 4

Pixel Multiplex Control

ZERO SHOULD

BE WRITTEN TO

THIS BIT

RESERVED*

ADV7160 Datasheet(PDF) 29 Page - Analog Devices

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