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CT1820 Datasheet(PDF) 7 Page - Aeroflex Circuit Technology |
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CT1820 Datasheet(HTML) 7 Page - Aeroflex Circuit Technology |
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7 / 10 page ![]() Aeroflex Circuit Technology SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700 7 RECEIVE CYCLE OPERATION DECODER SHIFT CLOCK (DSC) (see Figure 5) operates at the data rate (1MHz). When the DECODER recognises a valid sync and two valid Manchester data bits x, a receive cycle is initiated. The new sync is indicated at the COMMAND/DATA SYNC (C/D SYNC) output and the TAKE DATA output goes low y. The C/D sync output will remain in its valid state until a new sync is detected on a subsequent word or until DECODER RESET (DEC RST) or MRST goes low. A low at DEC RST or MRST causes C/D SYNC to go low. TAKE DATA remains low for 16 DSC periods during which time the 16 serial data bits appear at the SERIAL DATA OUTPUT (SDO). This data is simultaneously loaded into the first-rank receive register. The low-to-high transition of TAKE DATA z makes the new data available at the output of the second-rank receive register. This data remains available until the next low-to-high transitions of TAKE DATA. It is not reset or cleared by any other signals. This data is applied to the D0 to D15 I/O bus by setting DATA SELECT lines low. After all data has been loaded into the receive registers, the data is checked for odd parity. A low on VALID WORD (VW) output z, indicates successful reception of a word without any Manchester or parity errors. For consecutive word receptions, VW will go high again in 3 to 3.5µs. In the absence of succeeding valid syncs, VW will return high in 20µs. A DEC RST (low) at any time will reset VW high. All decoded commands, including RT ENABLE (address recognition), BROADCAST and MODE CODE are enabled internally by VW and remain valid only as long as VW is low. For 8-BIT l/O subsystems (D0 tied to D8, through D7 tied to D15), data may be extracted in 8 BIT bytes by selectively activating DATA SELECT 1 and DATA SEL.ECT 2. For serial data systems, SERIAL DATA OUTPUT is available at the DSC rate from y to z. 0 1 2 3 4 5 16 17 18 19 0 1 2 3 4 5 16 17 18 19 ½ SYNC ½ SYNC 15 14 13 2 1 0 P ½ SYNC ½ SYNC 15 14 13 2 1 0 P ½ SYNC ½ SYNC 15 14 13 2 1 0 P ½ SYNC ½ SYNC 15 14 13 2 1 0 P FROM PREVIOUS WORD 15 4 3 2 1 0 15 4 3 2 1 0 4 3 2 1 FROM PREVIOUS WORD UNDEFINED VALID FOR CURRENT WORD VALID FOR CURRENT WORD UNDEFINED NOT VALID FROM PREVIOUS WORD OPTIONAL–HIGH = TRISTATE HI-Z AT D0 TO D15 OPTIONAL–HIGH = TRISTATE HI-Z AT D0 TO D15 NEW DATA VALID NOT VALID VALID NEW DATA OSC DATA IN DATA IN TAKE DATA C/D SYNC SDO VW DECODE COMMANDS SECOND-RANK REC’V DATA SELECT (see text) REGISTER CONTENT Figure 5 – Receive Cycle Timing |
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