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OR2C04A Datasheet(PDF) 133 Page - List of Unclassifed Manufacturers

Part # OR2C04A
Description  Field-Programmable Gate Arrays
PDF  192 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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OR2C04A Datasheet(HTML) 133 Page - List of Unclassifed Manufacturers

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Data Sheet
June 1999
ORCA Series 2 FPGAs
Lucent Technologies Inc.
133
Timing Characteristics (continued)
5-4633(F).a
C = controlled by configuration RAM.
Notes:
The parameters MUX_DEL, XOR_DEL, and ND_DEL include the delay through the LUT in F5A/F5B modes.
See Table 41 for an explanation of FDBK_DEL and OMUX_DEL.
Figure 54. Combinatorial PFU Timing
A[4:0], B[4:0]
A[4:0], B[4:0]
A[4:0], B[4:0]
F4*_DEL
(LUT)
PFU
4
F5*_DEL
(LUT)
2
(LUT)
2
C0
MUX_DEL
C
F[3:0]
F3, F0
F1
F2
O[4:0]
FDBK_DEL
XSW LINES
OUTPUT MUX
C0MUX_DEL, C0XOR_DEL, C0ND_DEL
XOR_DEL
ND_DEL



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