OR2C04A datasheet(138/192 Pages) ETC

138 / 192 page

Data Sheet

ORCA Series 2 FPGAs

June 1999

138

Lucent Technologies Inc.

Timing Characteristics (continued)

Note: Speed grades of -5, -6, and -7 are for OR2TxxA devices only.

5-3226(F).r4

Figure 55. Read Operation—Flip-Flop Bypass

5-3227(F).r4

Figure 56. Read Operation—LUT Memory Loading Flip-Flops

Table 35A. OR2CxxA and OR2TxxA Asynchronous Memory Read Characteristics (MA/MB Modes)

OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C

≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.

OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C

≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85°C.

Parameter

Symbol

Speed

Unit

-2

-3

-4

-5

-6

-7

Min Max Min Max Min Max Min Max Min Max Min Max

Read Operation (TJ = 85 °C, VDD = min):

Read Cycle Time

Data Valid after Address (A[3:0], B[3:0] to F[3:0])

TRC

MEM*_ADEL

5.1

—

4.0

3.6

—

2.8

2.7

—

2.1

2.4

—

1.7

2.3

—

1.4

2.0

—

1.3

Read Operation, Clocking Data into Latch/Flip-flop

(TJ = 85 °C, VDD = min):

Address to Clock Setup Time (A[3:0], B[3:0] to CK)

Clock to PFU Out (CK to Q[3:0])—Register

MEM*_ASET

REG_DEL

2.4

—

2.4

1.8

—

2.0

1.2

—

1.9

1.1

—

1.5

1.0

—

1.3

1.0

—

1.0

Table 35B. OR2TxxB Asynchronous Memory Read Characteristics (MA/MB Modes)

OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C

≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85°C.

Parameter

Symbol

Speed

Unit

-7

-8

Min

Max

Min

Max

Read Operation (TJ = 85 °C, VDD = min):

Read Cycle Time

Data Valid after Address (A[3:0], B[3:0] to F[3:0])

TRC

MEM*_ADEL

1.9

—

1.3

1.8

—

1.0

Read Operation, Clocking Data into Latch/Flip-flop

(TJ = 85 °C, VDD = min):

Address to Clock Setup Time (A[3:0], B[3:0] to CK)

Clock to PFU Out (CK to Q[3:0])—Register

MEM*_ASET

REG_DEL

0.9

—

1.0

0.8

—

1.0

A[3:0], B[3:0]

F[3:0]

MEM*_ADEL

TRC

A[3:0], B[3:0]

MEM*_ASET

REG_DEL

Q[3:0]

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