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OR2C04A Datasheet(PDF) 145 Page - List of Unclassifed Manufacturers |
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OR2C04A Datasheet(HTML) 145 Page - List of Unclassifed Manufacturers |
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145 / 192 page  Data Sheet June 1999 ORCA Series 2 FPGAs Lucent Technologies Inc. 145 Timing Characteristics (continued) 1. Readback of the configuration bit stream when simultaneously writing to a PFU in either SSPM fast mode or SDPM fast mode is not allowed. 2. Because the setup time of data into the latches/FFs is less than 0 ns, data written into the RAM can be loaded into a latch/FF in the same PFU on the next opposite clock edge (one-half clock period). Note: Speed grades of -5, -6, and -7 are for OR2TxxA devices only. Table 39A. OR2CxxA and OR2TxxA Synchronous Memory Write Characteristics (SSPM and SDPM Modes) OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C. OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C. Parameter Symbol Speed Unit -2 -3 -4 -5 -6 -7 Min Max Min Max Min Max Min Max Min Max Min Max Write Operation for Fast-RAM Mode1: Maximum Frequency Clock Low Time Clock High Time Clock to Data Valid (CK to F[3:0])2 FFSCK TFSCL TFSCH FMEMS_DEL 38.2 13.1 13.1 — — — — 9.0 52.6 9.5 9.5 — — — — 7.4 83.3 6.0 6.0 — — — — 6.2 90.9 5.5 5.5 — — — — 5.0 92.6 5.4 5.4 — — — — 5.3 96.2 5.2 5.2 — — — — 5.2 MHz ns ns ns Write Operation for Normal RAM Mode: Maximum Frequency Clock Low Time Clock High Time Clock to Data Valid (CK to F[3:0]) FSCK TSCL TSCH MEMS_DEL 24.3 20.6 20.6 — — — — 10.9 33.3 15.0 15.0 — — — — 8.6 52.6 9.5 9.5 — — — — 7.5 58.0 8.5 8.5 — — — — 6.0 58.8 8.5 8.5 — — — — 6.4 59.8 8.4 8.4 — — — — 5.9 MHz ns ns ns Write Operation Setup Time: Address to Clock (A[3:0]/B[3:0] to CK) Data to Clock (WD[3:0] to CK) Write Enable (WREN) to Clock (A4 to CK) Write-port Enable (WPE) to Clock (C0 to CK) MEMS_ASET MEMS_DSET MEMS_WRSET MEMS_PWRSET 0.0 0.0 0.0 0.0 — — — — 0.0 0.0 0.0 0.0 — — — — 0.0 0.0 0.0 0.0 — — — — 0.0 0.0 0.0 0.0 — — — — 0.0 0.0 0.0 0.0 — — — — 0.0 0.0 0.0 0.0 — — — — ns ns ns ns Write Operation Hold Time: Address to Clock (A[3:0]/B[3:0] to CK) Data to Clock (WD[3:0] to CK) Write Enable (WREN) to Clock (A4 to CK) Write-port Enable (WPE) to Clock (C0 to CK) MEMS_AHLD MEMS_DHLD MEMS_WRHLD MEMS_PWRHLD 3.8 3.8 3.8 3.3 — — — — 3.0 3.0 3.0 2.3 — — — — 2.2 2.2 2.2 1.5 — — — — 2.0 2.0 2.0 1.4 — — — — 1.9 1.9 1.9 1.9 — — — — 1.8 1.8 1.8 1.2 — — — — ns ns ns ns Table 39.B OR2TxxB Synchronous Memory Write Characteristics (SSPM and SDPM Modes) OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85°C. Parameter Symbol Speed Unit -7 -8 Min Max Min Max Write Operation for Fast-RAM Mode1: Maximum Frequency Clock Low Time Clock High Time Clock to Data Valid (CK to F[3:0])2 FFSCK TFSCL TFSCH FMEMS_DEL 97.7 5.1 5.1 — — — — 5.1 112.4 4.5 4.5 — — — — 4.5 MHz ns ns ns Write Operation for Normal RAM Mode: Maximum Frequency Clock Low Time Clock High Time Clock to Data Valid (CK to F[3:0]) FSCK TSCL TSCH MEMS_DEL 60.8 8.2 8.2 — — — — 5.1 69.9 7.2 7.2 — — — — 4.5 MHz ns ns ns |
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